Memory device with platinum-rhodium stack as an oxygen barrier

Abstract

The present invention relates to an electrically conductive film stack for semiconductors and methods and apparatus for providing same. A film stack comprising a first layer of a platinum-rhodium alloy deposited by metal organic chemical vapor deposition (MOCVD) in the presence of a reducer, such as hydrogen (H 2 ) gas, and a second layer of the platinum-rhodium alloy deposited in the presence of an oxidizing gas, such as ozone (O 3 ), provides an electrical conductor that is also a relatively good barrier to oxygen. The platinum-rhodium film stack can be used as an electrode or capacitor plate for a capacitor with a high-k dielectric material. The electrode formed with alternating reducing and oxidizing agents produces a rough surface texture, which enhances the memory cell capacitance.

1 . An integrated circuit memory device with a plurality of capacitors, wherein a capacitor comprises: 
 a first plate of platinum-rhodium alloy electrically connected to an active area of an underlying substrate of the memory device, wherein a first surface of the first plate of platinum-rhodium alloy has hemispherical grains with an average size between about 50 Å and about 1000 Å;    a second plate; and    a dielectric disposed between the second plate and the first surface of the first plate, where the dielectric has a relative permittivity of at least 5.    
   
   
       2 . The integrated circuit memory device as defined in  claim 1 , wherein the dielectric has a relative permittivity of at least 10.  
   
   
       3 . The integrated circuit memory device as defined in  claim 1 , wherein the dielectric is selected from tantalum oxide (Ta 2 O 5 ) or barium strontium titanate (BST) (Ba x Sr 1-x TiO 3 ).  
   
   
       4 . The integrated circuit memory device as defined in  claim 1 , wherein the first surface of the first plate of platinum-rhodium alloy has hemispherical grains with an average size between about 100 Å and about 500 Å.  
   
   
       5 . The integrated circuit memory device as defined in  claim 1 , wherein about 5% to 50% of the platinum-rhodium alloy is rhodium.  
   
   
       6 . The integrated circuit memory device as defined in  claim 1 , wherein about 10% to 40% of the platinum-rhodium alloy is rhodium.  
   
   
       7 . The integrated circuit memory device as defined in  claim 1 , wherein the integrated circuit memory device is embodied in a dynamic read only memory (DRAM) chip.  
   
   
       8 . A system comprising: 
 a memory device, where the memory device is configured to store data for the system, the memory device comprising:    a capacitor comprising: 
 a dielectric with a relative permittivity of at least 5;  
 a first plate of platinum-rhodium alloy electrically connected to an active area of an underlying substrate of the memory device, wherein a first surface of the first plate of platinum-rhodium alloy has hemispherical grains with an average size between about 50 Å and about 1000 Å; and  
 a second plate adjacent the dielectric such that the dielectric is disposed between the first surface of the first plate and the second plate.  
   
   
   
       9 . The system as defined in  claim 8 , wherein the dielectric has a relative permittivity of at least 10.  
   
   
       10 . The system as defined in  claim 8 , wherein the dielectric is selected from tantalum oxide (Ta 2 O 5 ) or barium strontium titanate (BST) (Ba x Sr 1-x TiO 3 ).  
   
   
       11 . The system as defined in  claim 8 , wherein the first surface of the first plate of platinum-rhodium alloy has hemispherical grains with an average size between about 100 Å and about 500 Å.  
   
   
       12 . The system as defined in  claim 8 , wherein about 5% to 50% of the platinum-rhodium alloy is rhodium.  
   
   
       13 . The system as defined in  claim 8 , wherein about 10% to 40% of the platinum-rhodium alloy is rhodium.  
   
   
       14 . A circuit comprising: 
 a substrate assembly with at least a semiconductor material; and    electrodes for capacitors of the substrate assembly, where at least one electrode for the capacitors comprises platinum-rhodium alloy electrically connected to an active area of an underlying substrate, where a surface of the electrode includes a rough surface texture with hemispherical grains with an average size between about 50 Å and about 1000 Å.    
   
   
       15 . The circuit as defined in  claim 14 , wherein the surface has hemispherical grains with an average size between about 100 Å and about 500 Å.  
   
   
       16 . A memory device, comprising: 
 a substrate assembly with at least a semiconductor material; and    electrodes for capacitors of the substrate assembly, where at least one electrode for the capacitors comprises platinum-rhodium alloy electrically connected to an active area of an underlying substrate, where a surface of the capacitor plate includes a rough surface texture, wherein about 5% to 50% of the platinum-rhodium alloy is rhodium.    
   
   
       17 . The memory device as defined in  claim 16 , wherein about 10% to 40% of the platinum-rhodium alloy is rhodium.  
   
   
       18 . The memory device as defined in  claim 16 , wherein the rough surface texture has hemispherical grains with an average size between about 50 Å and about 1000 Å;  
   
   
       19 . The memory device as defined in  claim 16 , wherein the rough surface texture has hemispherical grains with an average size between about 100 Å and about 500 Å.