US2005226234A1PendingUtilityA1

System having interfaces and switch that separates coherent and packet traffic

48
Individually held — no corporate assignee on recordPriority: Nov 20, 2001Filed: Jun 7, 2005Published: Oct 13, 2005
Est. expiryNov 20, 2021(expired)· nominal 20-yr term from priority
Inventors:Barton SanoJoseph B. RowlandsJames B. KellerLaurent MollKoray OnerManu Gulati
H04L 49/90H04L 49/901H04L 49/9063G06F 13/28H04L 49/3009G06F 12/0813H04L 49/9073H04L 49/103
48
PatentIndex Score
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References
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Claims

Abstract

An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

Claims

exact text as granted — not AI-modified
1 - 13 . (canceled)  
   
   
       14 . A method comprising: 
 receiving packets and coherency commands on one or more interfaces;    routing the packets and the coherency commands through a switch, wherein the packets are routed to a packet direct memory access (DMA) circuit and the coherency commands are routed to a memory bridge;    the memory bridge generating transactions on an interconnect in response to at least some of the coherency commands; and    the packet DMA circuit generating transactions on the interconnect to write the packets to a memory.    
   
   
       15 . The method as recited in  claim 14  further comprising: 
 the memory bridge receiving transactions initiated by coherent agents on the interconnect;    the memory bridge generating coherency commands in response to at least some of the transactions initiated by the coherent agents; and    routing the coherency commands generated by the memory bridge for transmission on at least one of the one or more interfaces.    
   
   
       16 . The method as recited in  claim 14  further comprising: 
 the packet DMA circuit generating read transactions on the interconnect to read packets from the memory; and    routing the packets from the packet DMA circuit for transmission on at least one of the one or more interfaces.    
   
   
       17 . The method as recited in  claim 14  further comprising: 
 receiving noncoherent commands from the interfaces; and    routing the noncoherent commands to the memory bridge.    
   
   
       18 . (canceled)

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