Internal voltage generation circuit of semiconductor memory device

Abstract

Disclosed herein is an internal voltage generation circuit of a semiconductor memory device which is capable of supplying voltages of different levels to a column path & control logic and data path & control logic in the memory device according to different operation modes of the memory device. The column path & control logic and data path & control logic are applied with a normal operating voltage when they are involved in the current operation mode of the memory device, whereas with a lower voltage when they are not involved. Therefore, the present invention has the effect of efficiently managing internal voltages of the semiconductor memory device and reducing current leakage of the memory device and, in turn, unnecessary power consumption thereof.

1 . An internal voltage generation circuit of a semiconductor memory device comprising: 
 reference voltage generation means for generating a reference voltage as a control signal for internal voltage supply;    first internal voltage generation means for generating a first internal voltage of a desired level in response to said reference voltage from said reference voltage generation means; and    second internal voltage generation means responsive to an enable signal resulting from a logical operation of an active control signal indicative of an active mode and a refresh control signal indicative of a refresh mode and said reference voltage from said reference voltage generation means, for generating a second internal voltage of the same level as that of said first internal voltage when said memory device is in said active mode and a third internal voltage of a level lower than that of said first internal voltage when said memory device is in any other mode including said refresh mode.    
   
   
       2 . The internal voltage generation circuit as set forth in  claim 1 , wherein said first internal voltage is supplied to a row path & control logic in said memory device and said second and third internal voltages are supplied to a column path & control logic and a data path & control logic in said memory device.  
   
   
       3 . The internal voltage generation circuit as set forth in  claim 1 , wherein said first internal voltage generation means includes: 
 current mirror amplification means for comparing said first internal voltage with said reference voltage to obtain a difference therebetween and amplifying the obtained difference; and    pull-up means for raising the level of said first internal voltage to that of said reference voltage if it becomes lower than the level of said reference voltage.    
   
   
       4 . The internal voltage generation circuit as set forth in  claim 1 , wherein said second internal voltage generation means includes: 
 current mirror amplification means responsive to said enable signal for, only when said memory device is in said active mode, comparing said second internal voltage with said reference voltage to obtain a difference therebetween and amplifying the obtained difference;    pull-up means for raising the level of said second internal voltage to that of said reference voltage if it becomes lower than the level of said reference voltage; and    a MOS (Metal-Oxide Semiconductor) diode for generating said third internal voltage of the level lower than that of said first internal voltage at an output terminal of said second internal voltage generation means when said memory device is in any other mode including said refresh mode.    
   
   
       5 . The internal voltage generation circuit as set forth in  claim 1 , wherein: 
 said first internal voltage generation means includes:    first current mirror amplification means for comparing said first internal voltage with said reference voltage to obtain a difference therebetween and amplifying the obtained difference; and    first pull-up means for raising the level of said first internal voltage to that of said reference voltage if it becomes lower than the level of said reference voltage; and    said second internal voltage generation means includes:    second current mirror amplification means responsive to said enable signal for, only when said memory device is in said active mode, comparing said second internal voltage with said reference voltage to obtain a difference therebetween and amplifying the obtained difference;    second pull-up means for raising the level of said second internal voltage to that of said reference voltage if it becomes lower than the level of said reference voltage; and    a MOS diode for generating said third internal voltage of the level lower than that of said first internal voltage at an output terminal of said second internal voltage generation means when said memory device is in any other mode including said refresh mode.    
   
   
       6 . An internal voltage generation circuit of a semiconductor memory device comprising: 
 reference voltage generation means for generating a first reference voltage and a second reference voltage as control signals for internal voltage supply, 
 first internal voltage generation means for generating a first internal voltage of a desired level in response to said first reference voltage from said reference voltage generation means;  
 reference voltage transfer means responsive to an enable signal resulting from a logical operation of an active control signal indicative of an active mode and a refresh control signal indicative of a refresh mode and said first and second reference voltages from said reference voltage generation means, for transferring said first reference voltage when said memory device is in said active mode and said second reference voltage when said memory device is in any other mode including said refresh mode; and  
 second internal voltage generation means responsive to an output voltage from said reference voltage transfer means for generating a second internal voltage of the same level as that of said first internal voltage if the output voltage is said first reference voltage and a third internal voltage of a level lower than that of said first internal voltage if the output voltage is said second reference voltage.  
   
   
   
       7 . The internal voltage generation circuit as set forth in  claim 6 , wherein said first internal voltage is supplied to a row path & control logic in said memory device and said second and third internal voltages are supplied to a column path & control logic and a data path & control logic in said memory device.  
   
   
       8 . The internal voltage generation circuit as set forth in  claim 6 , wherein said first internal voltage generation means includes: 
 current mirror amplification means for comparing said first internal voltage with said first reference voltage to obtain a difference therebetween and amplifying the obtained difference; and    pull-up means for raising the level of said first internal voltage to that of said first reference voltage if it becomes lower than the level of said first reference voltage.    
   
   
       9 . The internal voltage generation circuit as set forth in  claim 6 , wherein said second internal voltage generation means includes: 
 current mirror amplification means for comparing said second (or third) internal voltage with said first (or second) reference voltage to obtain a difference therebetween and amplifying the obtained difference; and    pull-up means for raising the level of said second (or third) internal voltage to that of said first (or second) reference voltage if it becomes lower than the level of said first (or second) reference voltage.    
   
   
       10 . The internal voltage generation circuit as set forth in  claim 6 , wherein: 
 said first internal voltage generation means includes:    first current mirror amplification means for comparing said first internal voltage with said first reference voltage to obtain a difference therebetween and amplifying the obtained difference; and    first pull-up means for raising the level of said first internal voltage to that of said first reference voltage if it becomes lower than the level of said first reference voltage; and    said second internal voltage generation means includes:    second current mirror amplification means for comparing said second (or third) internal voltage with said first (or second) reference voltage to obtain a difference therebetween and amplifying the obtained difference; and    second pull-up means for raising the level of said second (or third) internal voltage to that of said first (or second) reference voltage if it becomes lower than the level of said first (or second) reference voltage.    
   
   
       11 . An internal voltage generation circuit of a semiconductor memory device comprising: 
 reference voltage generation means for generating a first reference voltage and a second reference voltage as control signals for internal voltage supply;    first internal voltage generation means for generating a first internal voltage of a desired level in response to said first reference voltage from said reference voltage generation means;    internal voltage transfer means responsive to an enable signal resulting from a logical operation of an active control signal indicative of an active mode and a refresh control signal indicative of a refresh mode for, when said memory device is in said active mode, receiving said first internal voltage from an output terminal of said first internal voltage generation means and outputting a second internal voltage of the same level as that of said first internal voltage to an output terminal of second internal voltage generation means; and    said second internal voltage generation means responsive to said enable signal and said second reference voltage from said reference voltage generation means for generating a third internal voltage of a level lower than that of said first internal voltage when said memory device is in any other mode including said refresh mode.    
   
   
       12 . The internal voltage generation circuit as set forth in  claim 11 , wherein said first internal voltage is supplied to a row path & control logic in said memory device and said second and third internal voltages are supplied to a column path & control logic and a data path & control logic in said memory device.  
   
   
       13 . The internal voltage generation circuit as set forth in  claim 11 , wherein said first internal voltage generation means includes: 
 current mirror amplification means for comparing said first internal voltage with said first reference voltage to obtain a difference therebetween and amplifying the obtained difference; and    pull-up means for raising the level of said first internal voltage to that of said first reference voltage if it becomes lower than the level of said first reference voltage.    
   
   
       14 . The internal voltage generation circuit as set forth in  claim 11 , wherein said second internal voltage generation means includes: 
 current mirror amplification means responsive to said enable signal for, only when said memory device is in any other mode including said refresh mode, comparing said third internal voltage with said second reference voltage to obtain a difference therebetween and amplifying the obtained difference; and    pull-up means for raising the level of said third internal voltage to that of said second reference voltage if it becomes lower than the level of said second reference voltage.    
   
   
       15 . The internal voltage generation circuit as set forth in  claim 11 , wherein: 
 said first internal voltage generation means includes:    first current mirror amplification means for comparing said first internal voltage with said first reference voltage to obtain a difference therebetween and amplifying the obtained difference; and    first pull-up means for raising the level of said first internal voltage to that of said first reference voltage if it becomes lower than the level of said first reference voltage; and    said second internal voltage generation means includes:    second current mirror amplification means responsive to said enable signal for, only when said memory device is in any other mode including said refresh mode, comparing said third internal voltage with said second reference voltage to obtain a difference therebetween and amplifying the obtained difference; and    second pull-up means for raising the level of said third internal voltage to that of said second reference voltage if it becomes lower than the level of said second reference voltage.    
   
   
       16 . An internal voltage generation circuit of a semiconductor memory device comprising: 
 internal voltage generation means for supplying a first internal voltage of a desired level to a row path & control logic; and    internal voltage transfer means for receiving said first internal voltage from said internal voltage generation means and, in response to an enable signal resulting from a logical operation of an active control signal indicative of an active mode and a refresh control signal indicative of a refresh mode, supplying a second internal voltage of the same level as that of said first internal voltage to a column path & control logic and a data path & control logic when said memory device is in said active mode and a third internal voltage of a level lower than that of said first internal voltage to said column path & control logic and data path & control logic when said memory device is in any other mode including said refresh mode,    wherein said internal voltage transfer means includes:    a MOS transistor for supplying said second internal voltage of the same level as that of said first internal voltage in response to said enable signal; and    a MOS diode for dropping said first internal voltage by a predetermined threshold voltage thereof and supplying the resulting voltage as said third internal voltage.    
   
   
       17 . The internal voltage generation circuit as set forth in  claim 16 , wherein said MOS transistor is a PMOS (P-channel Metal-Oxide Semiconductor) transistor, said PMOS transistor being turned on when said active control signal goes high in level and said refresh control signal goes low in level.  
   
   
       18 . The internal voltage generation circuit as set forth in  claim 16 , wherein said MOS diode is an NMOS (N-channel Metal-Oxide Semiconductor) diode.