High speed low power input buffer

Abstract

The input buffer circuit includes an input stage providing a switching point voltage based on a predetermined switching point set between a first and second reference voltages that maximizes the high and low noise margins of the input buffer. The input buffer circuit further includes an output stage. The output stage is coupled to the input stage. The output stage receives the switching point voltage from the input stage and amplifies the switching point voltage to a full logic level voltage.

1 . A method of operating an input buffer, comprising: 
 applying a first source voltage to a drain of a first NMOS transistor and applying a first sink voltage to a drain of a first PMOS transistor;    applying an input voltage higher than a switching point to a gate of the first NMOS transistor and to a gate of the first PMOS transistor;    increasing a gate to source voltage of the first NMOS transistor and increasing a source to gate voltage of a second PMOS transistor having a low reference voltage connected to the gate;    increasing current flow through the first NMOS, the second PMOS transistor, and to a second sink voltage; and    increasing the voltage to a gate of a second NMOS transistor and connecting an output of the input buffer to a third sink voltage.    
   
   
       2 . The method of operating an input buffer of  claim 1 , wherein the first sink voltage and the second sink voltage are the same voltage.  
   
   
       3 . The method of operating an input buffer of  claim 1 , wherein the third sink voltage is a ground voltage level.  
   
   
       4 . The method of operating an input buffer of  claim 1 , wherein first and second sink voltages are higher than the third sink voltage.  
   
   
       5 . The method of operating an input buffer of  claim 1 , wherein a difference between the first source voltage and the first sink voltage is less than 100 millivolts.  
   
   
       6 . A method of operating an input buffer, comprising: 
 applying a first source voltage to a drain of a first NMOS transistor;    applying a first sink voltage to a drain of a first PMOS transistor;    applying an input voltage lower than a switching point to a gate of the first NMOS transistor and to a gate of the first PMOS transistor;    decreasing a gate to source voltage of the first PMOS transistor and decreasing a source to gate voltage of a third NMOS transistor having a high reference voltage connected to the gate;    increasing current flow between the drain of the third NMOS transistor and a second source voltage through the first PMOS transistor to the first sink voltage; and    decreasing a voltage to a gate of a second PMOS transistor and connecting an output of the input buffer to a third source voltage.    
   
   
       7 . The method of operating an input buffer of  claim 6 , wherein the first source voltage and the second source voltage are the same voltage.  
   
   
       8 . The method of operating an input buffer of  claim 6 , wherein the third source voltage is a power supply voltage level.  
   
   
       9 . The method of operating an input buffer of  claim 6 , wherein first and second source voltages are lower than the third source voltage.  
   
   
       10 . The method of operating an input buffer of  claim 6 , wherein a difference between the first source voltage and the first sink voltage is less than 100 millivolts.  
   
   
       11 . The method of operating an input buffer of  claim 6 , wherein applying an input voltage includes setting the switching point voltage by sizing the first and second NMOS transistors and the first and second PMOS transistors.  
   
   
       12 . A method of operating an input buffer, comprising: 
 applying a first source voltage to a drain of a first NMOS transistor and applying a first sink voltage to a drain of a first PMOS transistor;    applying an input voltage to a gate of the first NMOS transistor and to a gate of the first PMOS transistor, wherein the input voltage is applied across the gate to drain of each of the first NMOS and first PMOS transistor;    wherein applying an input voltage higher than a switching point increases a gate to source voltage of the first NMOS transistor and increases a source to gate voltage of a second PMOS transistor having a low reference voltage connected to the gate; 
 resulting in increased current flow in a third PMOS transistor connected between the drain of the first NMOS transistor and the first source voltage and having a gate connected to the drain of the first NMOS transistor;  
 resulting in a current increase in the first NMOS transistor, the second PMOS transistor, and a second NMOS transistor connected between the source of the second PMOS transistor and a second sink voltage, and having a gate connected to a drain of the first PMOS transistor; and  
 resulting in an increase in the voltage to a gate of a third NMOS transistor and connecting an output of the input buffer to a third sink voltage; and  
   wherein applying an input voltage lower than the switching point decreases a gate to source voltage of the first PMOS transistor and decreases a source to gate voltage of a fourth NMOS transistor having a high reference voltage connected to the gate; 
 resulting in increased current flow in a fourth PMOS transistor connected between the drain of the fourth NMOS transistor and a second source voltage and having a gate connected to the drain of the first NMOS transistor;  
 resulting in a current increase in the first PMOS transistor, a fifth NMOS transistor connected between a drain of the first PMOS transistor and a second sink voltage and having a gate connected to the drain of the first PMOS transistor; and  
 resulting in a decrease in the voltage to a gate of a fifth PMOS transistor and connecting the output of the input buffer to a third source voltage.  
   
   
   
       13 . The method of operating an input buffer of  claim 12 , wherein the third sink voltage is a ground reference voltage level.  
   
   
       14 . The method of operating an input buffer of  claim 12 , wherein the third source voltage is a supply voltage level.  
   
   
       15 . The method of operating an input buffer of  claim 12 , wherein the first and second source voltages are the same voltage.  
   
   
       16 . The method of operating an input buffer of  claim 12 , wherein the first and second sink voltages are the same voltage.  
   
   
       17 . The method of operating an input buffer of  claim 12 , wherein the first and second source voltages are lower than the third source voltage level.  
   
   
       18 . The method of operating an input buffer of  claim 12 , wherein the first and second sink voltages are higher than the third sink voltage level.  
   
   
       19 . The method of operating an input buffer of  claim 12 , wherein the first and second source voltages are the same voltage and lower than the third source voltage, and the first and second sink voltages are the same voltage and higher than the third sink voltage level.  
   
   
       20 . The method of operating an input buffer of  claim 19 , wherein a difference between the first and second source voltage level and the first and second sink voltage level is 100 millivolts and is less than a difference between the third source voltage level and the third sink voltage level.  
   
   
       21 . The method of operating an input buffer of  claim 12 , wherein the high and the low reference voltages are selected to set the switching point to an average of the first source voltage level and the first sink voltage level.  
   
   
       22 . A method of operating an input buffer, comprising: 
 applying an input voltage having a voltage range between a high input logic level and a low input logic level of less than  100  millivolts to a first CMOS pair connected between a first source voltage level and a first sink voltage level;    wherein the first CMOS pair are cross coupled source to source to a second CMOS pair connected between a second source voltage level and a second sink voltage level;    wherein the second CMOS pair includes a high reference voltage communicating with a gate of a NMOS transistor of the second CMOS pair, and a low reference voltage communicating with a gate of a PMOS transistor of the second CMOS pair;    a drain of the PMOS transistor of the second CMOS pair communicating with a gate of a NMOS transistor communicating between a ground voltage and an output terminal of a third CMOS pair, and a drain of a NMOS transistor of the second CMOS pair communication with a gate of a PMOS transistor communicating between a supply voltage and the output terminal of the third CMOS pair; and    inverting and amplifying the input voltage logic level as an output logic level ranging between a high output logic level and a low output logic level of approximately 1000 millivolts.    
   
   
       23 . The method of operating an input buffer of  claim 22 , wherein the high and the low reference voltages are selected to set a logic switching point between the low input logic level and the high input logic level to an average of the first source voltage level and the first sink voltage level.  
   
   
       24 . The method of operating an input buffer of  claim 22 , wherein the first and second source voltages are lower than the supply voltage level.  
   
   
       25 . The method of operating an input buffer of  claim 22 , wherein the first and second sink voltages are higher than the ground voltage level.  
   
   
       26 . The method of operating an input buffer of  claim 22 , wherein the first and second source voltages are substantially equal to each other.  
   
   
       27 . The method of operating an input buffer of  claim 22 , wherein the first and second sink voltages are substantially equal to each other.  
   
   
       28 . The method of operating an input buffer of  claim 22 , wherein the source of a PMOS transistor of the first CMOS pair is connected to a source of the NMOS transistor of the second CMOS pair.  
   
   
       29 . The method of operating an input buffer of  claim 22 , wherein the source of a NMOS transistor of the first CMOS pair is connected to a source of the PMOS transistor of the second CMOS pair.