Semiconductor device and its manufacture method

Abstract

The disclosure pertains to a semiconductor device and its manufacture method, the semiconductor device including non-volatile memory cells and a peripheral circuit including field effect transistors having an insulated gate. A semiconductor device and its manufacture method are to be provided, the semiconductor device having memory cells with a high retention ability and field effect transistors having an insulated gate with large drive current. The semiconductor device has a semiconductor substrate ( 1 ) having first and second areas (AR 1 , AR 2 ), a floating gate structure ( 4, 5, 6, 7, 8 ) for a non-volatile memory cell, a control gate structure ( 14 ) formed coupled to the floating gate structure, formed in the first area, and an insulated gate electrode ( 12, 14 ) for a logical circuit formed in the second area, wherein the floating gate structure has bird's beaks larger than those of the insulated gate electrode.

1 . A semiconductor device comprising: 
 a semiconductor substrate having on a surface thereof a first element area and a second element area;    a first transistor having a first gate structure of a double gate type, formed at least in said first element area, said first gate structure including a control gate, and a floating gate whose side walls are covered with a thermally oxidized film, and having gate bird's beaks of a first length; and    a second transistor having a second gate structure having a gate electrode, formed in said second element area, and having no gate bird's beak or gate bird's beaks of a second length shorter than the first length,    wherein said first transistor operates as a non-volatile memory cell capable of electrically writing and erasing data and said second transistor operates as a logical circuit element.    
     
     
         2 . The semiconductor device according to  claim 1 , wherein said semiconductor substrate further comprises a third area, further comprising a third gate structure for controlling the non-volatile memory cell, said third gate structure including another gate electrode formed above said third area and a gate insulating film thicker than a gate insulating film of said second gate structure.  
     
     
         3 . The semiconductor device according to  claim 1 , wherein said floating gate includes an insulating lamination of an oxide film, a nitride film and an oxide film including interfaces therebetween, said control gate includes a silicon layer formed above said insulating lamination, side walls of said nitride film and said silicon layer are covered with said thermally oxidized film continuous with said bird's beaks, and said gate electrode of said second gate structure includes an electrode layer made of a same silicon layer as said silicon layer of said control gate.  
     
     
         4 . The semiconductor device according to  claim 1 , wherein said floating gate includes a first gate insulating film formed above said first area and a first silicon layer formed on said first gate insulating film, said control gate includes a second gate insulating film formed on said first silicon layer and a second silicon layer formed on said second gate insulating film, and side walls of said first and second gate insulating films are covered with said thermally oxidized film continuous with said bird's beaks.  
     
     
         5 . The semiconductor device according to  claim 1 , wherein said semiconductor substrate further comprises a third area, said control gate includes a low resistance region formed in said third area, and said floating gate extends from an area above said first area to and an area above said third area.  
     
     
         6 . A method for manufacturing a semiconductor device, comprising the steps of: 
 (a) forming an isolation region in a semiconductor substrate to define first and second areas;    (b) forming a lamination for use as a floating gate on said first area;    (c) forming a lamination of a gate electrode conductive layer and a masking insulating layer above said lamination for use as a floating gate and above said second area;    (d) pattering said masking insulating film in each gate electrode shape;    (e) while masking said second area, etching said gate electrode conductive layer and said lamination for use as a floating gate in said first area by using said masking insulating layer as an etching mask, to pattern a floating gate structure and a control gate structure;    (f) forming an oxide film on side walls of at least said floating gate structure; and    (g) while masking said first area, etching said gate electrode conductive layer in said second area by using said masking insulating layer as an etching mask, to pattern an insulated gate structure.    
     
     
         7 . The method for manufacturing a semiconductor device according to  claim 6 , wherein said step (b) stacks a tunneling oxide film, a first silicon layer and an upper gate insulating film or forms an insulating lamination of a tunneling oxide film and an upper nitride film.  
     
     
         8 . The method for manufacturing a semiconductor device according to  claim 6 , wherein said step (a) defines also a third area, and said step (c) forms a gate insulating film having a first thickness in said second area and a gate insulting film having a second thickness thicker than said first thickness in said third area, and stacking said gate electrode conductive layer and said masking insulating layer on said gate insulating films.  
     
     
         9 . The method for manufacturing a semiconductor device according to  claim 8 , wherein said step (e) etches said gate electrode conductive layer also in said third area by using said masking insulating layer as an etching mask to pattern a high voltage insulated gate electrode, and said step (f) forms an oxide film also on side walls of said high voltage insulated gate electrode.  
     
     
         10 . A method for manufacturing a semiconductor device, comprising the steps of: 
 (a) forming an isolation region in a semiconductor substrate to define first, second and third areas;    (b) forming a low resistance region in said second area;    (c) forming a lamination of an insulating film, a conductive layer and a masking insulating layer on said first, second and third areas;    (d) patterning said masking insulating layer in a floating gate electrode shape extending above said first and second areas and an insulated gate shape on said third area;    (e) while masking said third area, etching said conductive layer in said first and second areas by using said masking insulating layer as an etching mask to pattern a floating gate electrode extending from an area above said first area to an area above said second area;    (f) forming an oxide film on side walls of said floating gate structure; and    (g) while masking said first and second areas, etching said conductive layer in said third area by using said masking insulating film as an etching mask, to pattern an insulated gate electrode.