Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure
Abstract
A wiring structure to effectively reduce the wiring capacitance, and a method of forming the wiring structure is disclosed. In one embodiment, an underlying film having a dielectric constant than that of silicon oxide is formed on at least on side surfaces of the wires of a wiring layer and a low dielectric constant film having a further lower dielectric constant is formed between the wires. Further the surfaces of the underlying film are positively sloped. Because the low dielectric constants of the underlying film and the low dielectric constant film, the wiring capacitance is effectively reduced. Further, the positively sloped surfaces facilitate the filling of narrow spaces between the wires by the low dielectric constant film.
Claims
exact text as granted — not AI-modified1 . A method of forming a wiring structure for use in a semiconductor integrated circuit, comprising the steps of:
forming an intra-layer dielectric layer, including a low dielectric constant film having a dielectric constant lower than that of silicon oxide, over a semiconductor substrate, the intra-layer dielectric layer having a groove formed in the low dielectric constant film; forming side wall films having a second dielectric constant that is lower than that of silicon oxide, the side wall films formed on side walls of the groove; and forming a wiring layer including a wire formed in the groove.
2 . The method according to claim 1 , wherein the dielectric constant of the low dielectric constant film is lower than the second dielectric constant of the side wall films.
3 . The method according to claim 1 , wherein the step of forming side wall films includes depositing a fluorinated silicon oxide film by high density plasma chemical vapor deposition.
4 . The method according to claim 3 , wherein the high density plasma chemical vapor deposition is performed so that the fluorinated silicon oxide film contains substantially no Si(—F) 2 bonds.
5 . The method according to claim 1 , wherein the dielectric constant of the low dielectric constant film is 3.2 or less.
6 . The method according to claim 1 , wherein the dielectric constant of the low dielectric constant film is 3.0 or less.
7 . The method according to claim 1 , wherein the dielectric constant of the low dielectric constant film is 2.0 or less.
8 . A method of forming a wiring structure for use in a semiconductor integrated circuit, comprising the steps of:
forming an intra-layer dielectric layer, including a low dielectric constant film having a dielectric constant lower than that of silicon oxide, over a semiconductor substrate, the intra-layer dielectric layer having a groove formed in the low dielectric constant film; forming side wall films on side walls of the groove; and forming a wiring layer including a wire in the groove, wherein the side walls of the groove are substantially vertical with respect to a main surface of the semiconductor substrate, and surfaces of the side wall films are positively sloped.
9 . The method according to claim 8 , wherein substantial portions of the surfaces of the side wall films are positively sloped.
10 . The method according to claim 8 , wherein the step of forming side wall films includes performing high density plasma chemical vapor deposition with a substrate bias.
11 . The method according to claim 8 , wherein the step of forming a wiring layer includes forming at least one of a barrier layer and a seed layer by ionized sputtering.
12 . The method according to claim 8 , wherein a dielectric constant of the side wall films is lower than the dielectric constant of silicon oxide.
13 . The method according to claim 12 , wherein the dielectric constant of the low dielectric constant film is lower than the dielectric constant of the side wall films.
14 . The method according to claim 8 , wherein the dielectric constant of the low dielectric constant film is 3.2 or less.
15 . The method according to claim 8 , wherein the dielectric constant of the low dielectric constant film is 3.0 or less.
16 . The method according to claim 8 , wherein the dielectric constant of the low dielectric constant film is 2.0 or less.
17 . A method of forming a wiring structure for use in a semiconductor integrated circuit, comprising the steps of:
forming an intra-layer dielectric layer, including a low dielectric constant film having a dielectric constant lower than that of silicon oxide, over a semiconductor substrate, the intra-layer dielectric layer having a groove formed in the low dielectric constant film; forming side wall films on side walls of the groove; and forming a wiring layer including a wire in the groove, wherein a thickness of the side wall films on upper portions of the side walls of the groove is smaller than that on lower portions of the side walls.
18 . The method according to claim 17 , wherein the step of forming side wall films includes performing high density plasma chemical vapor deposition with a substrate bias.
19 . The method according to claim 17 , wherein the step of forming a wiring layer includes forming at least one of a barrier layer and a seed layer by ionized sputtering.
20 . The method according to claim 17 , wherein a dielectric constant of the side wall films is lower than that of silicon oxide.
21 . The method according to claim 20 , wherein the dielectric constant of the low dielectric constant film is lower than the dielectric constant of the side wall films.
22 . The method according to claim 17 , wherein the dielectric constant of the low dielectric constant film is 3.2 or less.
23 . The method according to claim 17 , wherein the dielectric constant of the low dielectric constant film is 3.0 or less.
24 . The method according to claim 17 , wherein the dielectric constant of the low dielectric constant film is 2.0 or less.Join the waitlist — get patent alerts
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