Non-volatile semiconductor memory device and method of fabricating the same

Abstract

There is provided a non-volatile semiconductor memory device exhibiting excellent electrical characteristics and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having two trenches, an isolation oxide film provided in the trench, a floating gate electrode, an ONO film, and a control gate electrode. The isolation oxide film has an upper surface with a region having a curvature protruding downward. The floating gate electrode has a flat upper surface and extends from a main surface of the semiconductor substrate between the two trenches to the two isolation oxide films. The ONO film extends from the upper surface of the floating gate electrode to a side surface of the floating gate electrode. The control gate electrode is provided on the ONO film to extend from the upper surface of the floating gate electrode to the side surface of the floating gate electrode.

1 - 4 . (canceled)  
   
   
       5 . A method of fabricating a non-volatile semiconductor memory device, comprising the steps of: providing a semiconductor substrate at a main surface with two spaced trenches; providing in said trench an isolation insulator having a protrusion protruding upper than a main surface of said semiconductor substrate; 
 isotropically etching away said protrusion partially to reduce said protrusion to be smaller in width than said trench;    after the step of isotropically etching, providing said semiconductor substrate at the main surface with a conductor film extending from a region located between said two isolation insulators to said isolation insulator;    removing an upper surface layer of said conductor film to expose an upper portion of said isolation insulator to provide a floating electrode formed of said conductor film, having a flat upper surface and located between said isolation insulators; and    etching away the upper portion of said isolation insulator adjacent to said floating electrode to expose a side surface of said floating electrode.    
   
   
       6 . The method according to  claim 5 , wherein: 
 the step of providing said semiconductor substrate at the main surface with said two spaced trenches includes the step of providing on the main surface of said semiconductor substrate a mask layer formed of stacked layers including a buffer conductor film layer, and having an open pattern positioned on a region to be provided with said two trenches, and the step of anisotropically etching the main surface of said semiconductor substrate with said mask layer used as a mask to partially remove the main surface of said semiconductor substrate to form said two trenches, in said mask layer said buffer conductor film layer being partially exposed to a side surface defining said open pattern;    the step of providing said isolation insulator includes the step of thermally oxidizing a side surface of said two trenches with said mask layer in existence to provide a first oxide film forming said isolation insulator, and the step of providing a second oxide film forming said isolation insulator on said first oxide film to fill said two trenches; and    the step of isotropically etching away includes the step of removing said mask layer.    
   
   
       7 . The method according to  claim 5 , wherein the step of providing said semiconductor substrate at the main surface with said two spaced trenches includes the steps of: 
 providing on the main surface of said semiconductor substrate a mask layer having an open pattern positioned on a region to be provided with said two trenches;    providing a sidewall film on a sidewall of said mask layer defining said open pattern;    with said mask layer and said sidewall film used as a mask, anisotropically etching the main surface of said semiconductor substrate away partially to provide said two trenches.    
   
   
       8 . The method according to  claim 5 , said semiconductor substrate including a memory cell region provided with a memory cell having said floating electrode and a peripheral circuitry region corresponding to a region other than said memory cell region, comprising the steps of: providing another trench in said peripheral circuitry region at the main surface of said semiconductor substrate; and 
 providing in said another trench another isolation insulator having a protrusion protruding upper than the main surface of said semiconductor substrate, wherein in the step of etching away, said another isolation insulator underlying a protection film has the upper portion etched away.