System and method for aligning internal transmit and receive clocks

Abstract

A system includes a master device connected to one or more slave devices via a channel, the channel communicating an externally generated first system clock towards the master device. A delay locked loop circuit receives the first system clock and a second phase feedback signal as inputs and generates a transmit clock signal. A phase offset circuit receives the transmit system clock and generates a phase shifted version of the transmit clock signal as a second system clock. A first phase detector receives a receive system clock and the transmit system clock and generates a first phase feedback signal. A delay element receives the first system clock and the first phase feedback signal and generates a delayed first system clock. A second phase detector receives the delayed first system clock and the second system clock and generates the second phase feedback signal.

1 . A method of aligning clock signals in a system comprising a master and one or more slave devices connected via a channel, the system further comprising a first system clock propagating towards the master and a second system clock propagating away from the master, and the master further comprising a transmitter and a receiver, the method comprising: 
 generating a transmit clock signal in the master, wherein data is driven onto the channel in relation to the transmit clock signal; and    adjusting the phase of the transmit clock signal in the master while maintaining a first predetermined phase relationship between the transmit clock signal and the second system clock.    
   
   
       2 . A method of aligning clock signals in a system comprising a master and one or more slave devices connected via a channel, the system further comprising a first system clock propagating towards the master and a second system clock propagating away from the master, the method comprising: 
 generating a transmit clock signal in the master in relation to the first system clock;    shifting a phase of the transmit clock signal phase by a predefined offset; and    passing the phase shifted transmit clock signal through an output driver circuit in the master to generate the second system clock, such that the first and second system clocks are not phase aligned.