Method for stabilizing or offsetting voltage in an integrated circuit

Abstract

A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.

1 . A method of applying a stable voltage to a column or row line of a memory device, comprising: 
 forming an amplifier connected to the column line or row line;    forming a capacitor connected to an input of the amplifier;    forming circuitry to charge the capacitor to an opposite polarity of the offset voltage to nullify the offset voltage of the amplifier, wherein forming the capacitor comprises: 
 depositing at least one layer of conductive material on a substrate; and  
 removing material from the layer of conductive material to form a first portion and second portion arranged in a predetermined pattern relative to one another to provide a maximum amount of juxtaposed surface area between the first and second portions.  
   
   
   
       2 . A method of applying a stable voltage to a column or row line of a memory device, comprising: 
 forming an amplifier connected to the column line or row line;    forming a capacitor connected to an input of the amplifier;    forming circuitry to charge the capacitor to an opposite polarity of the offset voltage to nullify the offset voltage of the amplifier, wherein forming the capacitor comprises: 
 depositing at least one layer of conductive material on a substrate; and  
 removing material from the layer of conductive material to form a first portion and second portion arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per area of the substrate.  
   
   
   
       3 . A method of applying a stable voltage to a column or row line of a memory device, comprising: 
 forming an amplifier connected to the column line or row line;    forming a capacitor connected to an input of the amplifier; and    forming circuitry to charge the capacitor to an opposite polarity of the offset voltage to nullify the offset voltage of the amplifier, wherein forming the capacitor comprises: 
 depositing at least one layer of conductive material;  
 removing a portion of the at least one layer of conductive material to form a first substantially comb-like structure including a plurality of teeth; and  
 removing another portion of the at least one layer of conductive material to form a second substantially comb-like structure including a plurality of teeth, wherein the teeth of the second substantially comb-like structure are interleaved with the teeth of the first substantially comb-like structure, and wherein each tooth of the first and second comb-like structures have a pair of sidewalls, each sidewall having a selected surface area and each of the teeth of the first comb-like structure and the second comb-like structure being separated by a gap of a chosen width to provide a predetermined capacitance.  
   
   
   
       4 . A method of applying a stable voltage to a column or row line of a memory device, comprising: 
 connecting an amplifier to the column line or row line;    connecting a capacitor to an input of the amplifier;    forming circuitry to charge the capacitor to an opposite polarity of the offset voltage to nullify the offset voltage of the amplifier, wherein the capacitor comprises:    a first substantial comb-like structure of conductive material including a plurality of teeth; and    a second substantially comb-like structure of conductive material including a plurality of teeth, wherein the teeth of the second substantially comb-like structure are interleaved with the teeth of the first substantially comb-like structure, and wherein each tooth of the first and second comb-like structures have a pair of sidewalls, each sidewall having a selected surface area and each of the teeth of the first comb-like structure and the second comb-like structure being separated by a gap of a chosen width to provide a predetermined capacitance.    
   
   
       5 . A method for connecting offset voltage in an amplifier, comprising: 
 applying a first timing signal that connects an output of the amplifier to a first input of the amplifier, connects a first plate of an offset capacitor to the first input, connects a second plate of the offset capacitor to a second input of the amplifier and ground;    delaying for a predetermined delay;    after the predetermined delay, disconnecting the output of the amplifier from the first input, disconnecting the first plate from the first input, and disconnecting the second plate from ground; and    applying a second timing signal to connect input signal to the amplifier.    
   
   
       6 . The method of  claim 5 , wherein delaying for the predetermined time includes charging the offset capacitor to the value of the offset voltage with an opposite polarity.  
   
   
       7 . The method of  claim 5 , wherein applying the first signal includes connecting a substantially comb-like first plate of the offset capacitor to the first input, and connecting a substantially comb-like second plate of the offset capacitor to the second input and ground.  
   
   
       8 . The method of  claim 7 , wherein connecting the substantially comb-like first plate and connecting a substantially comb-like second plate include arranging the first plate and the second plate in a predetermined pattern relative to one another to provide a maximum amount of capacitance per area of a semiconductor die.  
   
   
       9 . The method of  claim 7 , wherein connecting the substantially comb-like first plate and connecting a substantially comb-like second plate include arranging the first plate and the second plate in a predetermined pattern relative to one another to provide a maximum amount of juxtaposed surface area between the first plate and the second plate.  
   
   
       10 . A method for correcting an offset voltage in an amplifier on a semiconductor die, comprising: 
 connecting an output of the amplifier to a first switch;    connecting an inverting input of the amplifier to the first switch;    connecting a second switch to the inverting input;    connecting a third switch to the non-inverting input of the amplifier and ground;    connecting an offset capacitor, which includes a first portion and a second portion arranged in a pattern to maximize capacitance per semiconductor die area, between the second switch and the non-inverting input;    disconnecting the inverting input and non-inverting input from an input signal; and    closing the first, second, and third switches to charge the capacitor to the offset voltage.    
   
   
       11 . The method of  claim 10 , wherein disconnecting the inverting input and the non-inverting input include opening input switches between an input signal and the inverting input and the capacitor.  
   
   
       12 . The method of  claim 10 , wherein closing the first, second, and third switches includes holding the first, second, and third switches closed for a time period sufficient to fully charge the capacitor.  
   
   
       13 . The method of  claim 10 , wherein closing the first, second, and third switches includes opening the first, second, and third switches after a time delay and applying an input signal to the inverting input and the capacitor to produce an output from the amplifier that is independent of frequency and the amplifier offset voltage.  
   
   
       14 . The method of  claim 13 , wherein applying the input signal includes applying a magnetic random access memory signal to the inverting input and the capacitor.  
   
   
       15 . The method of  claim 14 , wherein applying the magnetic random access memory signal includes applying a signal to drive column lines of a magnetic random access memory device.  
   
   
       16 . A method, comprising: 
 providing an input circuit, which has an offset voltage, to a memory device;    providing a memory connected to the input circuit;    correcting the offset voltage of the input circuit, wherein correcting the offset voltage includes: 
 connecting an output of an amplifier of the input circuit to an inverting input of the amplifier;  
 connecting the inverting terminal to an offset capacitor;  
 connecting the offset capacitor to a non-inverting input of the amplifier;  
 connecting the non-inverting input to ground;  
 charging the offset capacitor to the offset voltage;  
 after a time period, disconnecting the output from the inverting input;  
 after the time period, disconnecting the inverting input from the offset capacitor;  
 after the time period, disconnecting the non-inverting input from ground;  
   applying an input signal to the non-inverting input and the offset capacitor; and    outputting a signal from the output to the memory.    
   
   
       17 . The method of  claim 16 , wherein outputting the signal includes outputting a signal corrected for the offset voltage of the amplifier and independent of the frequency of the input signal.  
   
   
       18 . The method of  claim 16 , wherein applying the input signal includes applying a column-line control signal to the amplifier.  
   
   
       19 . The method of  claim 18 , wherein outputting the signal includes outputting a column-line drive signal from the output of the amplifier.  
   
   
       20 . The method of  claim 19 , wherein outputting the column-line drive signal includes outputting the column-line drive signal to a magnetic random access memory (MRAM).  
   
   
       21 . The method of  claim 20 , wherein outputting the column-line drive signal includes outputting the column-line signal to a multiplexor which is connected to a plurality of column lines.  
   
   
       22 . The method of  claim 16 , wherein charging the capacitor includes charging a first portion that has a first plurality of teeth and grounding a second portion that has a second plurality of teeth interleaved with the first plurality of teeth to provide a maximum amount of juxtaposed surface area between the first and second portions.