Semiconductor apparatus, manufacturing method thereof, semiconductor module apparatus using semiconductor apparatus, and wire substrate for semiconductor apparatus

Abstract

A semiconductor apparatus of the present invention includes: (i) a wire substrate having an insulating substrate in which a plurality of wire patterns are provided, (ii) a semiconductor element installed on the wire substrate with the insulating resin interposed therebetween, and a plurality of connecting terminals provided in the semiconductor element are electrically connected to connecting terminals of the wire patterns, respectively. In the semiconductor apparatus, the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns, and an entire upper face of each of the mark patterns is covered with the insulating resin.

1 . A semiconductor apparatus comprising: (i) a wire substrate including an insulating substrate on which a plurality of wire patterns are provided; and (ii) a semiconductor element installed on the wire substrate with an insulating resin interposed therebetween, 
 a plurality of connecting terminals provided in the semiconductor element being electrically connected to connecting terminals of the wire patterns, respectively,    wherein:    the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns, and    an entire upper face of each of the mark patterns is covered with the insulating resin.    
     
     
         2 . The semiconductor apparatus as set forth in  claim 1 , wherein: 
 the insulating resin wholly covers a solder resist aperture portion that exposes the connecting terminals of the wire patterns, the solder resist aperture portion being provided in a solder resist covering the wire patterns.    
     
     
         3 . The semiconductor apparatus as set forth in claim  1 , wherein: 
 the mark patterns are provided in a semiconductor element installation region on the insulating substrate, the semiconductor element installation region overlapping with the insulating resin.    
     
     
         4 . The semiconductor apparatus as set forth in  claim 3 , wherein: 
 the insulating resin wholly covers a solder resist aperture portion that exposes the connecting terminals of the wire patterns, the solder resist aperture portion being provided in a solder resist covering the wire patterns.    
     
     
         5 . The semiconductor apparatus as set forth in  claim 1 , wherein: 
 the mark patterns are provided within a solder resist aperture portion that exposes the connecting terminals of the wire patterns, the solder resist aperture portion being provided in a solder resist covering the wire patterns.    
     
     
         6 . The semiconductor apparatus as set forth in  claim 5 , wherein: 
 the insulating resin wholly covers the solder resist aperture portion that exposes the connecting terminals of the wire patterns, the solder resist aperture portion being provided in the solder resist covering the wire patterns.    
     
     
         7 . The semiconductor apparatus as set forth in  claim 1 , wherein: 
 the mark patterns are provided in a formation region of a fillet formed, by the insulating resin, outside a solder resist aperture portion that exposes the connecting terminals of the wire patterns, the solder resist aperture portion being provided in a solder resist covering the wire patterns.    
     
     
         8 . The semiconductor apparatus as set forth in  claim 7 , wherein: 
 when viewed from above, the solder resist aperture portion has a shape defined by (i) line segments, each of which intersects with the wire patterns provided in a long length direction of the semiconductor element, and each of which extends along an installation site region of the wire patterns, (ii) line segments, each of which intersects with the wire patterns extending in a short length direction of the semiconductor element, and each of which extends along the installation site region of the wire patterns, and (iii) linkage attaining line segments, each of which connects adjacent ones of the line segments such that the linkage attaining line segment extends in an inner side with respect to each intersection point of respective extension lines of the line segments,    the mark patterns are formed outside the solder resist aperture portion and oppose the respective linkage attaining line segments.    
     
     
         9 . The semiconductor apparatus as set forth in  claim 7 , wherein: 
 when viewed from above, the solder resist aperture portion has a substantially octagon shape, two sides of the solder resist aperture portion intersecting with the wire patterns provided in a long length direction of the semiconductor element, the two sides extending along an installation site region of the wire patterns, and the two sides being longer than other sides, and    the mark patterns are so provided as to oppose respective oblique sides of the solder resist aperture portion, the oblique sides opposing corners of the semiconductor element.    
     
     
         10 . A semiconductor module apparatus comprising: 
 a semiconductor apparatus including: (i) a wire substrate including an insulating substrate on which a plurality of wire patterns are provided; and (ii) a semiconductor element installed on the wire substrate with an insulating resin interposed therebetween, a plurality of connecting terminals provided in the semiconductor element being electrically connected to connecting terminals of the wire patterns, respectively, wherein: the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns; and an entire upper face of each of the mark patterns is covered with the insulating resin.    
     
     
         11 . A method for manufacturing a semiconductor apparatus including: (i) a wire substrate including an insulating substrate on which a plurality of wire patterns are provided; and (ii) a semiconductor element installed on the wire substrate with an insulating resin interposed therebetween, a plurality of connecting terminals provided in the semiconductor element being electrically connected to connecting terminals of the wire patterns, respectively, wherein: the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns; and an entire upper face of each of the mark patterns is covered with the insulating resin, 
 the method comprising the steps of:    providing the insulating resin on the insulating substrate such that the insulating resin covers an entire surface of each of the mark patterns; and    detecting the mark pattern via the insulating resin provided on the mark pattern, and aligning the connecting terminals of the semiconductor element with the connecting terminals of the wire patterns.    
     
     
         12 . A wire substrate for use in a semiconductor apparatus including: (i) the wire substrate including an insulating substrate on which a plurality of wire patterns are provided; and (ii) a semiconductor element installed on the wire substrate with an insulating resin interposed therebetween, a plurality of connecting terminals provided in the semiconductor element being electrically connected to connecting terminals of the wire patterns, respectively, wherein: the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns; and an entire upper face of each of the mark patterns is covered with the insulating resin, 
 the wire substrate, comprising:    the mark patterns, for use in alignment of (i) the connecting terminals of the wire patterns and (ii) the connecting terminals of the semiconductor element to be installed in the insulating substrate, the mark patterns being provided within a solder resist aperture portion that exposes the connecting terminals of the wire patterns, the solder resist aperture portion being formed in a solder resist covering the wire patterns provided on the insulating substrate.    
     
     
         13 . A wire substrate for use in a semiconductor apparatus including: (i) the wire substrate including an insulating substrate on which a plurality of wire patterns are provided; and (ii) a semiconductor element installed on the wire substrate with an insulating resin interposed therebetween, a plurality of connecting terminals provided in the semiconductor element being electrically connected to connecting terminals of the wire patterns, respectively, wherein: the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns; and an entire upper face of each of the mark patterns is covered with the insulating resin, and 
 the semiconductor apparatus further including a solder resist aperture portion of a solder resist covering the wire patterns provided in the insulating substrate, the solder resist aperture portion has a shape, when viewed from above, defined by (i) line segments, each of which intersects with the wire patterns provided in a long length direction of the semiconductor element installed on the insulating substrate, and each of which extends along an installation site region of the wire patterns, (ii) line segments, each of which intersects with the wire patterns extending in a short length direction of the semiconductor element, and each of which extends along an installation site region of the wire patterns, and (iii) linkage attaining line segments, each of which connect adjacent line segments of the line segments such that the linkage attaining line segment extends in an inner side with respect to each intersection point of respective extended lines of the line segments; and the mark pattern is formed outside the solder resist aperture portion and opposes the respective linkage attaining line segments,    said wire substrate, comprising:    the mark patterns for alignment of (i) the connecting terminals of the wire patterns and (ii) the connecting terminals of the semiconductor element to be installed in the insulating substrate, the mark patterns being provided outside the solder resist aperture portion such that the mark patterns oppose the respective linkage attaining line segments.