Multi-processor system and memory accessing method

Abstract

A multiprocessor system includes a plurality of microprocessors configured to operate on a plurality of operating systems, respectively, and a memory section configured to have a plurality of memory spaces respectively allocated to the plurality of microprocessors. Each of the plurality of microprocessors may include a translation look-aside buffer (TLB) and a page table register. The TLB stores a copy of at least a part of data of one of the plurality of memory spaces corresponding to the microprocessor, and the copy includes a relation of each of virtual addresses of a virtual address space and a corresponding physical address of a physical address space as the memory space. The page table register refers to the TLB in response to an execution virtual address generated based on an application program to be executed by the microprocessor to determine an execution physical address corresponding to the execution virtual address. The microprocessor accesses the memory space based on the execution physical address.

1 . A multiprocessor system comprising: 
 a plurality of microprocessors configured to operate on a plurality of operating systems, respectively; and    a memory section configured to have a plurality of memory spaces respectively allocated to said plurality of microprocessors.    
   
   
       2 . The multiprocessor system according to  claim 1 , wherein each of said plurality of microprocessors comprises: 
 a translation look-aside buffer (TLB) configured to store a copy of at least a part of data of one of said plurality of memory spaces corresponding to said microprocessor, said copy including a relation of each of virtual addresses of a virtual address space and a corresponding physical address of a physical address space as said memory space; and    a page table register configured to refer to said TLB in response to an execution virtual address generated based on an application program to be executed by said microprocessor to determine an execution physical address corresponding to said execution virtual address, and    said microprocessor accesses said memory space based on said execution physical address.    
   
   
       3 . The multiprocessor system according to  claim 2 , wherein a page table is provided for said memory space to store the relation of the virtual addresses and the corresponding physical address, and 
 said TLB stores the copy of said page table.    
   
   
       4 . The multiprocessor system according to  claim 3 , wherein said page table further stores an identifier to identify said operating system, and 
 said page table register of said microprocessor refers to said TLB to determine whether the stored identifier and said identifier held said microprocessor are coincident with each other, and refers to said TLB for translation of said execution virtual address into said execution physical address, when the stored identifier and said identifier held said microprocessor are coincident with each other.    
   
   
       5 . The multiprocessor system according to  claim 2 , wherein said microprocessor further comprises: 
 an address check circuit configured to generates a determination result to indicate whether or not said execution physical address meets a predetermined condition, and    when said determination result indicates that said execution physical address meets said predetermined condition, said microprocessor accesses said memory space based on said execution physical address.    
   
   
       6 . The multiprocessor system according to  claim 5 , wherein said predetermined condition is whether said execution physical address is in a range from an upper limit physical address to a lower limit physical address in said memory space.  
   
   
       7 . The multiprocessor system according to  claim 6 , wherein said microprocessor further comprises: 
 an upper limit & lower limit physical address storage section configured to store said upper limit physical address and said lower limit physical address.    
   
   
       8 . A memory access method comprising: 
 providing a plurality of microprocessors configured to operate on a plurality of operating systems, respectively, and a memory section configured to have a plurality of memory spaces allocated to said plurality of microprocessors; and    accessing an allocated memory space of said plurality of memory spaces by one of said plurality of microprocessors.    
   
   
       9 . The memory access method according to  claim 8 , wherein virtual addresses and physical addresses are allocated to each of said plurality of memory spaces, respectively, 
 said memory space has a page table configured to store a relation of each of said virtual addresses and a corresponding one of said physical addresses, and    said accessing comprises:    referring to said page table in said memory space in response to an execution virtual address to determine execution physical address corresponding to said execution virtual address; and    accessing said memory space based on said execution physical address.    
   
   
       10 . The memory access method according to  claim 8 , wherein said page table in said memory space stores an identifier to identify said memory space, and 
 said accessing comprises:    referring to said page table in the said memory space to determine whether the stored identifier and said identifier held said microprocessor are coincident with each other; and    when the stored identifier and said identifier held said microprocessor are coincident with each other, determining said execution physical address.    
   
   
       11 . The memory access method according to  claim 9 , wherein said microprocessor further comprises an address check circuit, and 
 said accessing comprises:    when said execution physical address is determined, generating a determination result from said address checking circuit to indicate whether or not said execution physical address meets a predetermined condition; and    when said determination result indicates that said execution physical address meets said predetermined condition, accessing said memory space based on said execution physical address.    
   
   
       12 . The memory access method according to  claim 11 , wherein said condition is a range from an upper limit physical address of said physical addresses allocated to said memory space to a lower limit physical address of said physical addresses, and 
 said accessing comprises:    when said execution physical address is determined, generating a determination result indicating whether or not said execution physical address is contained in said range; and    when said determination result indicates that said execution physical address is contained in said range, accessing said memory space based on said execution physical address.