Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture

Abstract

A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the first and second device features, and an external cover or enclosure disposed around at least a portion of the substrate and the conductive link. The package can be filled with a liquid or a pressurized gas to transfer heat away from the conductive link. In one embodiment, the enclosure can have a composition substantially identical to the composition of the conductive links and the enclosure can be formed simultaneously with formation of the conductive link to reduce the number of process steps required to form the microelectronic device package. A sacrificial material can temporarily support the conductive link during manufacture and can subsequently be removed to suspend at least a portion of the conductive link between two points.

1 - 62 . (canceled)  
   
   
       63 . A method for manufacturing a microelectronic device package, comprising: 
 forming at least one microelectronic device feature at least proximate to a surface of a microelectronic substrate;    coupling a conductive link to the at least one microelectronic device feature of the microelectronic substrate;    disposing an enclosure around at least a portion of the microelectronic substrate;    sealing a gas within the enclosure and in contact with the conductive link with the gas at a pressure of at least one atmosphere above atmospheric pressure; and    exposing the enclosure to atmospheric pressure while the gas remains sealed within the enclosure.    
   
   
       64 . The method of  claim 63 , further comprising: 
 placing the microelectronic substrate, the enclosure, and the conductive link in an controlled pressure environment;    reducing a pressure within the controlled pressure environment to withdraw gas from the enclosure while the enclosure remains open to the controlled pressure environment;    elevating a pressure within the controlled pressure environment to be at least one atmosphere greater than atmospheric pressure while the enclosure remains open to the controlled pressure environment;    sealing the enclosure while the enclosure remains in the controlled pressure environment; and    removing the enclosure, the microelectronic substrate and the conductive link as a unit from the controlled pressure environment.    
   
   
       65 . The method of  claim 63  wherein the enclosure includes a contact structure having contacts with solder balls for electrically coupling the microelectronic substrate to other devices, and wherein the method further comprises bonding the solder balls to another device after sealing an aperture in the enclosure to seal the gas in the enclosure.  
   
   
       66 . The method of  claim 63  wherein the enclosure includes an aperture and sealing a gas within the enclosure includes disposing solder on a metallic ring disposed around the aperture, disposing a metallic lid on the solder, and elevating a temperature of the enclosure to bond the metallic lid to the metallic ring.  
   
   
       67 . The method of  claim 63 , further comprising selecting the gas disposed within the enclosure to include at least one of hydrogen and helium.  
   
   
       68 . The method of  claim 63  wherein placing the microelectronic substrate, the enclosure, and the conductive link in an elevated pressure environment includes placing the microelectronic substrate, the enclosure, and the conductive link in an elevated pressure environment having a pressure of from about 5 atmospheres to about 50 atmospheres above atmospheric pressure.  
   
   
       69 . The method of  claim 63  wherein the enclosure includes an aperture positioned to allow the gas to enter the enclosure and contact the conductive link, and wherein the method further comprises sealing the aperture before removing the enclosure from the elevated pressure environment.  
   
   
       70 . The method of  claim 63  wherein disposing the enclosure around the microelectronic substrate includes: 
 forming walls extending away from the microelectronic substrate;    forming a contact structure adjacent to the walls, the contact structure having at least one contact electrically coupled to the conductive link and configured to couple the microelectronic substrate to other components, the contact structure further having an aperture for receiving the gas in the enclosure; and    sealing the aperture in the contact structure after the gas enters the enclosure and before removing the enclosure from the elevated pressure environment.    
   
   
       71 . The method of  claim 63  wherein the enclosure includes a contact structure having electrical contacts for coupling the microelectronic package to other components, the enclosure further including walls between the contact structure and the microelectronic substrate, and wherein the method includes forming the walls to support a weight of the microelectronic substrate when the contact structure faces downwardly.  
   
   
       72 . The method of  claim 63 , further comprising disposing a foam material between the conductive link and an interior surface of the enclosure.  
   
   
       73 . The method of  claim 63 , further comprising selecting the gas to include a reducing agent.  
   
   
       74 . The method of  claim 63 , further comprising selecting the enclosure to include an electrically insulative material sealed to the microelectronic substrate.  
   
   
       75 . The method of  claim 63  wherein the microelectronic device feature is a first microelectronic device feature and the microelectronic substrate includes a second microelectronic device feature, and wherein the method further comprises suspending at least a portion of the conductive link between two points positioned between the first and second microelectronic device features.  
   
   
       76 . The method of  claim 63 , further comprising selecting the enclosure to include an electrically conductive material.  
   
   
       77 . The method of  claim 63 , further comprising selecting the enclosure to include at least one of copper, a copper alloy, aluminum and an aluminum alloy.  
   
   
       78 . The method of  claim 63 , further comprising selecting the enclosure to include at least one of silicon dioxide and silicon nitride.  
   
   
       79 . The method of  claim 63 , further comprising selecting the enclosure to include the same conductive as is included in the conductive link.  
   
   
       80 . The method of  claim 63 , further comprising forming at least a portion of the enclosure simultaneously with forming the conductive link.  
   
   
       81 . The method of  claim 63  wherein the at least one microelectronic device feature is coupled to a first bond site, and wherein the method further comprises: 
 supporting the microelectronic substrate with a support substrate; and    connecting the conductive link between the first bond site and a second bond site positioned on the support substrate.    
   
   
       82 . A method for manufacturing a microelectronic device package, comprising: 
 forming first and second microelectronic device features at least proximate to a surface of a microelectronic substrate;    coupling a conductive link between the first and second microelectronic device features of the microelectronic substrate;    removing a sacrificial material adjacent to the conductive link to suspend at least a portion of the conductive link between two points;    disposing an enclosure around at least a portion of the microelectronic substrate;    sealing a gas within the enclosure and adjacent to the conductive link; and    exposing the enclosure to a pressure at least five atmospheres less than a pressure within the enclosure while the gas remains sealed within the enclosure.    
   
   
       83 . The method of  claim 82 , further comprising: 
 disposing the sacrificial material on the microelectronic substrate;    forming a void in the sacrificial material, with a location of the void coinciding with a location of the conductive link; and    filling the void with conductive material to form the conductive link.    
   
   
       84 . The method of  claim 82 , further comprising forming at least a portion of the enclosure simultaneously with forming the conductive link by: 
 disposing the sacrificial material on the microelectronic substrate;    forming first and second voids in the sacrificial material with the first void corresponding a portion of the enclosure and the second void corresponding to the conductive link; and    filling the first and second voids to simultaneously form the external wall portion of the package and the conductive link.    
   
   
       85 . The method of  claim 82 , further comprising forming at least a portion of the enclosure and the conductive link simultaneously by: 
 disposing a first layer of a first component of the sacrificial material on the microelectronic substrate;    disposing a first layer of a second component of the sacrificial material on the first layer of the first component to form a first etch stop layer;    disposing a second layer of the first component on the first etch stop layer;    disposing a second layer of the second component on the second layer of the first component to form a second etch stop layer;    forming a first void in first layer of the first component with the first void corresponding to a portion of the enclosure and extending transverse to the surface of the microelectronic substrate;    forming a second void in the second layer of the first component with the second void corresponding to a portion of the enclosure extending transverse to the surface of the microelectronic substrate and a portion of the conductive link extending along an axis generally aligned with the surface of the microelectronic substrate; and    filling the first and second voids to simultaneously form the external wall portion of the package and the conductive link.    
   
   
       86 . The method of  claim 82 , further comprising selecting the sacrificial material to include at least one of a carbonaceous material, a polymer, a polyimide, a photoresist material, parylene, and parylene-C.  
   
   
       87 . The method of  claim 82 , further comprising selecting a material for the enclosure to be the same as a material for the conductive link.  
   
   
       88 . The method of  claim 82 , further comprising: 
 forming an internal support member inward from the enclosure and simultaneously with forming at least a portion of the enclosure; and    supporting the conductive link with the internal support member.    
   
   
       89 . The method of  claim 82 , further comprising selecting a thickness of the enclosure to support a weight of the package when the package is inverted with the microelectronic substrate facing upwardly.  
   
   
       90 . The method of  claim 82  wherein the enclosure includes an aperture positioned to allow the gas to enter the enclosure and contact the conductive link, and wherein the method further comprises sealing the aperture before removing the enclosure from the elevated pressure environment.  
   
   
       91 . The method of  claim 82  wherein sealing a gas within the enclosure includes disposing a metallic ring about an aperture in the enclosure, disposing a solder ring on the metallic ring, and soldering a metallic lid on the solder ring to at least restrict a flow of gas outwardly from the enclosure.  
   
   
       92 . The method of  claim 82 , further comprising forming the enclosure to include a contact structure having electrical contacts for coupling the microelectronic package to other components.  
   
   
       93 . A method for manufacturing a microelectronic device package, comprising: 
 forming first and second microelectronic device features at least proximate to a surface of a microelectronic substrate;    coupling a conductive link between the first and second microelectronic device features of the microelectronic substrate;    removing a sacrificial material adjacent to the conductive link to suspend at least a portion of the conductive link between two points;    disposing an enclosure around at least a portion of the microelectronic substrate; and    sealing a liquid within the enclosure and adjacent to the conductive link.    
   
   
       94 . The method of  claim 93 , further comprising selecting the liquid to include carbon tetrachloride.  
   
   
       95 . The method of  claim 93 , further comprising selecting the liquid to be generally electrically non-conductive.  
   
   
       96 . The method of  claim 93 , further comprising selecting the liquid to be an organic liquid.  
   
   
       97 . The method of  claim 93  wherein sealing the liquid within the enclosure includes disposing a metallic ring about an aperture in the enclosure, disposing a solder ring on the metallic ring, and soldering a metallic lid on the solder ring.  
   
   
       98 . The method of  claim 93 , further comprising forming the enclosure to include a contact structure having electrical contacts for coupling the microelectronic package to other components.  
   
   
       99 - 107 . (canceled)  
   
   
       108 . A microelectronic device package formed by a process that comprises: 
 forming first and second microelectronic device features at least proximate to a surface of a microelectronic substrate;    coupling a conductive link between the first and second microelectronic device features of the microelectronic substrate;    removing a sacrificial material adjacent to the conductive link to suspend at least a portion of the conductive link between two points;    disposing an enclosure around the microelectronic substrate;    placing the microelectronic substrate, the conductive link and the enclosure in an elevated pressure environment having a gas that includes hydrogen and/or helium at a pressure of from about 5 to about 50 atmospheres above atmospheric pressure while an interior of the enclosure remains in fluid communication with the elevated pressure environment;    sealing the gas within the enclosure and in thermal contact with the conductive link;    removing the microelectronic substrate, the conductive link and the enclosure as a unit from the elevated pressure environment and exposing the enclosure to atmospheric pressure.    
   
   
       109 . The package of  claim 108 , wherein the process further comprises forming at least a portion of the enclosure simultaneously with forming the conductive link by: 
 disposing the sacrificial material on the microelectronic substrate;    forming first and second voids in the sacrificial material with the first void corresponding to a portion of the enclosure and the second void corresponding to the conductive link; and    filling the first and second voids to simultaneously form the portion of the enclosure and the conductive link.    
   
   
       110 . A method for manufacturing a microelectronic device package, comprising: 
 forming at least one microelectronic device feature at least proximate to a surface of a microelectronic substrate;    electrically coupling the at least one microelectronic device feature to a first bond site;    engaging the microelectronic substrate with a support substrate having a second bond site;    coupling a conductive link between the first bond site and the second bond site;    disposing an enclosure around at least a portion of the microelectronic substrate;    sealing a gas within the enclosure and in contact with the conductive link with the gas at a pressure at least one atmosphere above atmospheric pressure; and    exposing the enclosure to atmospheric pressure while the gas remains sealed within the enclosure.    
   
   
       111 . The method of  claim 110  wherein sealing a gas includes sealing a gas at a pressure of from about 5 atmospheres to about 50 atmospheres above atmospheric pressure.  
   
   
       112 . The method of  claim 110 , further comprising: 
 placing the microelectronic substrate, the enclosure and the conductive link in an elevated pressure environment having a pressure at least one atmosphere greater than atmospheric pressure while the enclosure remains open to the elevated pressure environment;    sealing the enclosure while the enclosure remains in the elevated pressure environment; and    removing the enclosure, the microelectronic substrate and the conductive link as a unit from the elevated pressure environment.    
   
   
       113 . The method of  claim 110  wherein coupling the conductive link includes connecting a wire bond between the first bond site and the second bond site.  
   
   
       114 . The method of  claim 110  wherein coupling the conductive link includes connecting a solder ball between the first bond site and the second bond site.  
   
   
       115 . The method of  claim 110 , further comprising sealably attaching the enclosure to the support substrate.  
   
   
       116 . The method of  claim 110  wherein the conductive link is a first conductive link and the microelectronic device feature is a first microelectronic device feature, and wherein the method further comprises coupling a second conductive link between the first and second microelectronic device features.  
   
   
       117 . The method of  claim 110  wherein the conductive link is a first conductive link and the microelectronic device feature is a first microelectronic device feature, and wherein the method further comprises coupling a second conductive link between the first and second microelectronic device features, with at least a portion of the second conductive link between the first and second microelectronic device features being suspended between a first point and a second point.  
   
   
       118 . The method of  claim 110 , further comprising selecting the enclosure to include a metallic material.  
   
   
       119 . The method of  claim 110  wherein the enclosure is a first enclosure and wherein the method further comprises disposing a second enclosure within the first enclosure and adjacent to the microelectronic substrate.  
   
   
       120 . The method of  claim 110  wherein the enclosure is a first enclosure, the conductive link is a first conductive link, and the at least one microelectronic device feature includes a first microelectronic device feature, and wherein the microelectronic substrate has a second microelectronic device features, and wherein the method further comprises: 
 coupling a second conductive link between the first and second microelectronic device features;    disposing a second enclosure adjacent to the microelectronic substrate before disposing the first enclosure, the second enclosure having the first bond site positioned within the first enclosure; and    providing fluid communication between an interior region of the first enclosure and an interior region of the second enclosure to place the interior regions of the first and second enclosures at approximately the same pressure.    
   
   
       121 . A method for manufacturing a microelectronic device package, comprising: 
 forming microelectronic device features in a microelectronic substrate;    forming a sacrificial support structure by depositing a first polymer material on a surface of the microelectronic substrate, depositing a first oxide layer on the first polymer material, depositing a second polymer material on the first oxide and depositing a second oxide layer on the second polymer material;    selectively masking portions of the second oxide layer and selectively removing portions of the second oxide layer and the second polymer material to form first voids corresponding to locations of an external wall of the package and simultaneously form second voids corresponding to conductive links extending in a direction aligned with the surface of the microelectronic substrate;    selectively masking portions of the first oxide layer and selectively removing portions of the first oxide layer and the first polymer material to form third voids coupled to the first voids and simultaneously form fourth voids coupled to the second voids and extending in a direction transverse to the surface of the microelectronic substrate;    disposing a conductive material in the first and third voids to form a conductive link and simultaneously disposing the conductive material in the second and fourth voids to form a conductive external wall portion for the package;    planarizing the package to remove a portion of the conductive material; and    removing the sacrificial support structure adjacent to the conductive link to suspend a portion of the conductive link between two points.    
   
   
       122 . The method of  claim 121 , further comprising selecting the oxide to include silicon dioxide.  
   
   
       123 . The method of  claim 121  wherein removing the sacrificial support structure includes exposing the structure to a plasma.  
   
   
       124 . The method of  claim 121 , further comprising selecting the sacrificial material to include at least one of a polyimide and a photoresist material.  
   
   
       125 . The method of  claim 121 , further comprising selecting a material of the external wall portion and the conductive link to include at least one of copper and aluminum.  
   
   
       126 . The method of  claim 121  wherein the external wall portion is a first external wall portion and the conductive link is a first conductive link, and wherein the method further comprises: 
 simultaneously forming a second external wall portion of the package above the first external wall portion and a second conductive link above the first conductive link, the second external wall portion attached to the first external wall portion; and    removing material adjacent to the second conductive link simultaneously with removing material adjacent to the first conductive link to suspend at least a portion of the second conductive link.    
   
   
       127 . The method of  claim 121 , further comprising forming an internal heat transfer member inward from the external wall of the package and simultaneously with forming the external wall portion of the package.