Semiconductor device and method for manufacturing the same

Abstract

There is disclosed a semiconductor device which comprises a semiconductor substrate, a pair of element isolating insulating films separately formed in the semiconductor substrate and defining an element region, a pair of impurity diffusion regions formed in the element regions and in contact with the element isolating insulating films, respectively, a channel region interposed between the pair of impurity diffusion regions, and a gate electrode formed via a gate insulating film on the channel region, the gate electrode being disposed away from end portions of the impurity diffusion regions. The gate length of the gate electrode is limited to 30 nm or less, the distance between the impurity diffusion regions and the edges of the gate electrode is respectively limited to 10 nm or less, and the distribution in lateral direction of impurity concentration in the impurity diffusion regions is limited to 1 digit/3 nm or more.

1 - 11 . (canceled)  
   
   
       12 . A method of manufacturing a semiconductor device comprising: 
 separately forming a pair of element isolating insulating films to define an element region;    forming a gate electrode having a gate length of 30 nm or less via a gate insulating film on a channel region of said element region of semiconductor substrate;    forming an offset spacer on a sidewall of said gate electrode;    implanting an impurity into said semiconductor substrate with said offset spacer and said gate electrode being employed as a mask;    heat-treating said semiconductor substrate for a very short period of time to activate said impurity which has been introduced into said impurity diffusion region, the impurity which has been activated being substantially prevented from being introduced into a region below said gate electrode;    forming an interlayer insulating film over the entire top surface of said semiconductor substrate; and    forming a contact hole in said interlayer insulating film, said contact hole being subsequently filled with a conductive material to form a wiring.    
   
   
       13 . The method according to  claim 12 , wherein said heat-treating is performed for a period of 100 msec or less.  
   
   
       14 . The method according to  claim 12 , wherein said heat-treating is performed for a period of 10 msec or less.  
   
   
       15 . The method according to  claim 12 , wherein said heat-treating is performed for a period of 1 msec or less.  
   
   
       16 . The method according to  claim 12 , wherein said offset spacer has a thickness of 2 nm to 15 nm.  
   
   
       17 . The method according to  claim 12 , wherein said offset spacer is formed of TEOS.  
   
   
       18 . The method according to  claim 12 , further comprising, subsequent to forming said impurity diffusion region, obliquely implanting halo impurity into the channel region of said semiconductor substrate with said gate electrode and said offset spacer being employed as a mask, wherein the impurity concentration of the surface portion of said channel region is controlled to less than 2×10 18  cm −3 .  
   
   
       19 . The method according to  claim 12 , further comprising, prior to heat-treating, forming a gate sidewall on the sidewall of said offset spacer.  
   
   
       20 . The method according to  claim 19 , further comprising, subsequent to forming said gate sidewall, introducing said impurity into said semiconductor substrate to form a deep impurity diffusion region, wherein the impurity in said deep impurity diffusion region is substantially prevented from being introduced into a region below said gate electrode after heat-treating.