Architecture for mask programmable devices

Abstract

The present invention is directed to a semi-programmable ASIC using two metals for the metal layers. The semi-programmable ASIC may have a prefabricated first section and a customized second section. The prefabricated first section and the customized second section may each include one or more metal layers. The one or more metal layers included in the prefabricated first section may be used to define undifferentiated sets of electrical and logic elements. An undifferentiated set of electrical and logic elements may be a NAND logic gate, a NOR logic gate, or the like. The one or more metal layers included in the customized second section may be used to define logic functions of the undifferentiated sets of electrical and logic elements. The metal used in the one or more metal layers included in the prefabricated first section may be of one type such as copper, copper alloy, or the like, and the metal used in the metal layers included in the customized second section may be of another type such as aluminum, aluminum alloy, or the like.

1 . A semiconductor device, comprising: 
 an array of base cells formed with a substrate; and    at least one prefabricated metal layer formed over said array, said at least one prefabricated metal layer defining said base cells into undifferentiated sets of electrical and logic elements;    
     
     
         2 . The semiconductor device of  claim 1 , wherein said at least one prefabricated metal layer is made of a material selected from the group consisting of copper and copper alloy.  
     
     
         3 . The semiconductor device of  claim 1 , wherein said at least one prefabricated metal layer is made of a material selected from the group consisting of aluminum and aluminum alloy.  
     
     
         4 . The semiconductor device of  claim 1 , wherein said undifferentiated sets of electrical and logic elements are NAND gates.  
     
     
         5 . The semiconductor device of  claim 1 , wherein said undifferentiated sets of electrical and logic elements are NOR gates.  
     
     
         6 . The semiconductor device of  claim 1 , wherein said array of base cells is a sea-of-gates array.  
     
     
         7 . The semiconductor device of  claim 1 , wherein said array of base cells is a structured sea-of-gates array.  
     
     
         8 . A method for manufacturing a semiconductor device, comprising: 
 (a) forming transistors on a silicon wafer; and    (b) forming at least one metal layer over said transistors, said at least one metal layer defining said transistors into undifferentiated sets of electrical and logic elements.    
     
     
         9 . The method of  8 , wherein said at least one metal layer is made of a material selected from the group consisting of copper and copper alloy.  
     
     
         10 . The method of  8 , further comprising (c) customizing said semiconductor device using at least one other metal layer.  
     
     
         11 . The method of  10 , wherein said at least one other metal layer is made of a material selected from the group consisting of aluminum and aluminum alloy.  
     
     
         12 . The method of  10 , wherein said at least one other metal layer is made of a material selected from the group consisting of copper and copper alloy.