US2005210221A1PendingUtilityA1

Microcomputer and microcomputer system

Assignee: RENESAS TECH CORPPriority: Feb 16, 1999Filed: May 17, 2005Published: Sep 22, 2005
Est. expiryFeb 16, 2019(expired)· nominal 20-yr term from priority
Inventors:Naoki Mitsuishi
G06F 13/28G06F 13/16
49
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A microcomputer is provided with a data-transfer unit such as a DMA (direct memory access) controller for controlling a transfer of data through an external bus. Used in an access to an external device controlled by the data-transfer unit, a bus-interface means of the microcomputer includes a buffer-register means which can be specified as either a source location or a destination location of a data transfer. Thus, an internal-bus master such as a CPU employed in the microcomputer is capable of reading out information such as a packet command from the buffer-register means at a high speed through an internal bus without using the external bus and, hence, capable of carrying out an operation reflecting a transfer control condition specified by the packet command.

Claims

exact text as granted — not AI-modified
1 . A microcomputer comprising: 
 a storage means;    a data processing unit capable of making an access to said storage means through a first internal bus and used for executing an instruction;    a first data-transfer unit for controlling a transfer of data;    a bus-interface means capable of connecting said first internal bus or said first data-transfer unit to an external bus; and    a bus-control means for executing bus control and arbitrating requests for a bus-access right;    wherein:    said storage mans, said data processing unit, said first data-transfer unit and said bus-interface means are integrated in a single semiconductor chip; and    said bus-control means allows an operation to make an access only within said microcomputer by using said first internal bus to be carried out concurrently with an operation carried out by said first data-transfer unit to make an access to an external address space through said bus-interface means.    
   
   
       2 - 54 . (canceled)

Join the waitlist — get patent alerts

Track US2005210221A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.