US2005205986A1PendingUtilityA1

Module with integrated active substrate and passive substrate

Assignee: ICHITSUBO IKUROHPriority: Mar 18, 2004Filed: Mar 18, 2004Published: Sep 22, 2005
Est. expiryMar 18, 2024(expired)· nominal 20-yr term from priority
H10W 90/753H10W 72/5524H10W 72/5522H10W 72/5449H10W 72/5445H10W 72/932H10W 90/00H10W 76/40
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Claims

Abstract

Systems and methods are disclosed for a device having one or more active substrates comprising substantially transistors or diodes formed thereon; one of more passive substrate comprising substantially inductors, capacitors or resistors formed thereon; a plurality of bonding pads positioned on the active and passive substrates; and bonding wires connected to the bonding pads.

Claims

exact text as granted — not AI-modified
1 . A device, comprising: 
 one or more active substrates comprising substantially transistors or diodes formed thereon;    one or more passive substrates comprising substantially inductors, capacitors or resistors formed thereon;    a plurality of bonding pads positioned on the active and passive substrates; and    bonding wires connected to the bonding pads.    
     
     
         2 . The device of  claim 1 , further comprising a die pad to receive the active  10  and passive substrates.  
     
     
         3 . The device of  claim 2 , further comprising one or more pins and wherein one or more of the bonding wires connect one or more bonding pads to the one or more pins.  
     
     
         4 . The device of  claim 1 , wherein the substrates comprise gallium arsenide substrates.  
     
     
         5 . The device of  claim 1 , wherein the active substrate comprises supporting passive components.  
     
     
         6 . The device of  claim 1 , further comprising a substantially passive IC coupled to the active substrate.  
     
     
         7 . The device of  claim 1 , further comprising one or more substantially passive ICs for passive components only.  
     
     
         8 . The device of  claim 1 , wherein the substrates are interconnected with bonding wires.  
     
     
         9 . The device of  claim 1 , wherein the substrates are mounted on a metal die pad.  
     
     
         10 . The device of  claim 1 , wherein the substrates are encapsulated in molded plastics or other insulating medium.  
     
     
         11 . The device of  claim 1 , wherein the active substrates comprises primarily transistors.  
     
     
         12 . The device of  claim 11 , wherein the transistors include silicon bipolar, CMOS, RFCMOS, BICOMS, SiGe, GaAs HBT, or HEMT.  
     
     
         13 . The device of  claim 11 , wherein the transistors are fabricated on a wafer with semiconductor layer structure, junctions, and dopings.  
     
     
         14 . The device of  claim 1 , wherein the passive substrate comprises a network of resistor (R), inductor (L), and capacitor (C) without active device structure.  
     
     
         15 . The device of  claim 1 , wherein the passive substrate comprises one or more conductive metal layers for inductor (L) and interconnection.  
     
     
         16 . The device of  claim 1 , wherein the passive substrate comprises an insulating layer with suitable dielectric properties.  
     
     
         17 . The device of  claim 16 , wherein the insulating layer comprises Nitride or Oxide as the dielectric layer for a capacitor (C).  
     
     
         18 . The device of  claim 1 , wherein the passive substrate comprises a layer including TaN or NiCr for a resistor (R).  
     
     
         19 . The device of  claim 1 , wherein the passive substrate comprises one or more circuits of passive components including transmission lines, impedance matching network, filters, baluns, or diplexers.  
     
     
         20 . The device of  claim 1 , wherein the passive substrate is fabricated using fewer fabrication steps than the active substrate.

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