Trench transistor and method for fabricating a trench transistor with high-energy-implanted drain

Abstract

The invention relates to a method for fabricating a trench transistor, in which there are formed, within an epitaxial layer ( 11, 11 ′) deposited above a substrate ( 10 ) of a first conductivity type (n), a trench ( 14 ) and, within the trench ( 14 ), a gate dielectric ( 15 ) and a gate electrode ( 16 ) and, in a body region ( 20 ) of a second conductivity type (p) adjoining the trench ( 14 ) a source region ( 13 ) of the first conductivity type (n), a drift region ( 12 ) of the first conductivity type (n) forming a drain zone being formed at the end of the junction between the substrate ( 10 ) and the epitaxial layer ( 11, 11 ′) by means of one or more high-energy implantations, the lower end (U) of the trench ( 14 ) projecting into said drift region ( 12 ), and to a trench transistor of this type formed as a low-voltage transistor.

1 - 11 . (canceled)  
   
   
       12 . A method for fabricating a trench transistor, comprising: 
 providing an epitaxial layer disposed above a substrate, the substrate having a first conductivity type;    providing a trench and, within the trench, a gate dielectric and a gate electrode;    providing a body region of a second conductivity type adjoining the trench and a source region of the first conductivity type disposed within the body region; and    forming a drift region of the first conductivity type at the an of a junction between the substrate and the epitaxial layer using one or more high-energy implantations, a lower end of the trench disposed within said drift region, the drift region including at least a portion of a drain zone.    
   
   
       13 . The fabrication method as claimed in  claim 12 , wherein providing the epitaxial layer further comprises depositing the epitaxial layer such that the epitaxial layer has a second conductivity type and subsequently forms the body region.  
   
   
       14 . The fabrication method as claimed in  claim 12 , wherein providing the epitaxial layer further comprises providing the epitaxial layer having a first dopant concentration and subsequently forming the body region using the epitaxial layer, the body region having a second dopant concentration that is greater than the first dopant concentration.  
   
   
       15 . The fabrication method as claimed in  claim 12 , wherein the steps of forming the drift region and providing the body region occur prior to the step of providing the trench.  
   
   
       16 . The fabrication method as claimed in  claim 12 , wherein the step of providing the trench occurs before the steps of forming the drift region and providing the body region.  
   
   
       17 . The fabrication method as claimed in  claim 16 , further comprising planarizing the gate dielectric and the gate electrode prior to the step of forming the drift region.  
   
   
       18 . The fabrication method as claimed in  claim 12 , wherein forming the drift region further comprises using a high-energy implantation dose of approximately 10 13  cm −1  to 5·10 13  cm −2 .  
   
   
       19 . The fabrication method as claimed in  claim 12 , wherein the first conductivity type comprises an n-type and the second conductivity type comprises a p-type.  
   
   
       20 . The fabrication method as claimed in  claim 12 , wherein a doping concentration of the drift region is greater than a doping concentration of the body region.  
   
   
       21 . A trench transistor comprising: 
 a substrate having a first conductivity type;    an epitaxial layer disposed above the substrate;    a trench and, within the trench, a gate dielectric and a gate electrode;    a body region of a second conductivity type adjoining the trench, the body region having formed therein a source region of the first conductivity type; and    a drift region of the first conductivity type which forms a drain zone, the drift region disposed between the the substrate and the epitaxial layer and extending above and below a lower end of the trench, the drift region directly adjoining an underside of the body region.    
   
   
       22 . The trench transistor as claimed in  claim 21 , wherein the first conductivity type comprises an n-type and the second conductivity type comprises a p-type.  
   
   
       23 . The trench transistor as claimed in  claim 22 , wherein a doping concentration of the drift region is greater than a doping concentration of the body region.  
   
   
       24 . The trench transistor of as claimed in  claim 21 , wherein at least a portion of the epitaxial layer forms the body region.  
   
   
       25 . A method for fabricating a trench transistor, comprising: 
 providing an epitaxial layer disposed above a substrate, the substrate having a first conductivity type;    providing a trench configured to contain, at least in part, a gate dielectric and a gate electrode;    providing a source region of the first conductivity type within the epitaxial layer, the source region disposed adjacent the trench; and    forming a drift region of the first conductivity type using at least one implantation, such that the drift region is disposed directly above the substrate, the drift region extending above and below a lower end of the trench, the drift region including at least a portion of a drain zone.    
   
   
       26 . The fabrication method as claimed in  claim 25 , wherein providing the epitaxial layer further comprises depositing the epitaxial layer such that the epitaxial layer has a second conductivity type and subsequently forms a body region, and wherein the drift region is disposed between the body region and the substrate.  
   
   
       27 . The fabrication method as claimed in  claim 25 , wherein providing the epitaxial layer further comprises providing the epitaxial layer having a first dopant concentration and subsequently forming a body region using the epitaxial layer, the body region having a second dopant concentration that is greater than the first dopant concentration.  
   
   
       28 . The fabrication method as claimed in  claim 25 , wherein the steps of forming the drift region and providing the source region occur prior to the step of providing the trench.  
   
   
       29 . The fabrication method as claimed in  claim 25 , wherein the step of providing the trench occurs before the steps of forming the drift region and providing the source region.  
   
   
       30 . The fabrication method as claimed in  claim 29 , further comprising planarizing the gate dielectric and the gate electrode prior to the step of forming the drift region.  
   
   
       31 . The fabrication method as claimed in  claim 25 , wherein forming the drift region further comprises using an implantation dose of approximately 10 13  cm −2  to 5·10 13  cm −2 .