Non-volatile memory device having an asymmetrical gate dielectric layer and method of manufacturing the same

Abstract

In a memory device, and a method of manufacturing the same, the memory device includes a semiconductor substrate, a first impurity region and a second impurity region formed by injecting impurities into the semiconductor substrate, and a gate structure on the semiconductor substrate between the first impurity region and the second impurity region, the gate structure including a gate electrode and an asymmetric dielectric layer including a floating gate.

1 . A memory device, comprising: 
 a semiconductor substrate;    a first impurity region and a second impurity region formed by injecting impurities into the semiconductor substrate; and    a gate structure on the semiconductor substrate between the first impurity region and the second impurity region,    the gate structure comprising a gate electrode and an asymmetric dielectric layer including a floating gate.    
   
   
       2 . The memory device as claimed in  claim 1 , further comprising at least two sub-channels between the first and second impurity regions.  
   
   
       3 . The memory device as claimed in  claim 1 , wherein the asymmetric dielectric layer comprises: 
 a tunneling oxide layer on the semiconductor substrate between the first impurity region and the second impurity region;    the floating gate on the tunneling oxide layer; and    a blocking oxide layer on the floating gate.    
   
   
       4 . The memory device as claimed in  claim 3 , wherein at least one of the tunneling oxide layer and the blocking oxide layer has a varying thickness.  
   
   
       5 . The memory device as claimed in  claim 4 , wherein the blocking oxide layer comprises one or more steps formed therein.  
   
   
       6 . The memory device as claimed in  claim 3 , wherein the tunneling oxide layer comprises silicon oxide (SiO 2 ).  
   
   
       7 . The memory device as claimed in  claim 3 , wherein the floating gate comprises one selected from the group consisting of Si 2 N 4 , MO, MON, and MSiON, where M is metal.  
   
   
       8 . The memory device as claimed in  claim 7 , wherein the metal is selected from the group consisting of hafnium (Hf), zirconium (Zr), tantalum (Ta), aluminum (Al) and one of the lanthanide group.  
   
   
       9 . The memory device as claimed in  claim 3 , wherein the blocking oxide layer comprises one selected from the group consisting of Al 2 O 3  and SiO 2 .  
   
   
       10 . The memory device as claimed in  claim 3 , wherein the gate electrode comprises one selected from the group consisting of polysilicon, a metal, and a metal compound.  
   
   
       11 . The memory device as claimed in  claim 1 , further comprising spacers on sidewalls of the gate structure.  
   
   
       12 . A method of manufacturing a memory device, comprising: 
 forming a dielectric layer asymmetrically on a semiconductor substrate;    forming a gate structure by forming a gate electrode on the dielectric layer, and removing side portions of the gate structure to expose portions of the semiconductor substrate on both sides of the gate structure; and    forming a first impurity region to one side of the gate structure and a second impurity region to another side of the gate structure by injecting impurities into the exposed semiconductor substrate.    
   
   
       13 . The method as claimed in  claim 12 , wherein forming the dielectric layer comprises forming sequentially a tunneling oxide layer, a floating gate, and a blocking oxide layer on the semiconductor substrate.  
   
   
       14 . The method as claimed in  claim 13 , wherein forming the tunneling oxide layer, the floating gate, and the blocking oxide layer comprises forming at least one of the tunneling oxide layer and the blocking oxide layer to have a varying thickness.  
   
   
       15 . The method as claimed in  claim 14 , wherein forming the blocking oxide layer to have a varying thickness comprises forming one or more steps in the blocking oxide layer.  
   
   
       16 . The method as claimed in  claim 12 , further comprising: 
 forming spacers on sidewalls of the gate structure; and    injecting impurities into the side portions of the semiconductor substrate, thereby forming third and fourth impurity regions having higher impurity densities than the first and second impurity regions, respectively.    
   
   
       17 . The method as claimed in  claim 12 , wherein forming the dielectric layer asymmetrically comprises forming at least two sub-channels between the first and second impurity regions.