Random number test circuit, random number generation circuit, semiconductor integrated circuit, IC card and information terminal device

Abstract

A random number test circuit includes a counting unit to count number of repetitions of a certain-value bit in a random number sequence, the repetitions occurring in series, a detecting unit to detect a plurality of numbers corresponding to a kind of bits in the random number sequence, and a determining unit to determine whether the random number sequence is normal, based on the numbers.

1 . A random number test circuit comprising: 
 a counting unit configured to count number of repetitions of a certain-vasue bit in a random number sequence, the repetitions occurring in series;    a detecting unit configured to detect a plurality of numbers corresponding to a kind of bits in the random number sequence; and    a determining unit configured to determine whether the random number sequence is normal, based on the numbers.    
   
   
       2 . A random number generation circuit comprising: 
 a generation unit configured to generate the random number sequence; and    the random number test circuit according to  claim 1 , which tests the random number sequence.    
   
   
       3 . A random number test circuit comprising: 
 a receiving unit configured to receive a random number sequence;    a detection circuit configured to detect a plurality of bit data items of “1” or “0” in the random number sequence;    a shift register which holds in series the bit data items of “1” or “0” repeated in the random number sequence, based on the detected bit data items;    a register which holds, based on the detected bit data items, a content of the shift register when each of the bit data items is switched from “1” to “0” or from “0” to “1”; and    a determination circuit configured to determine types of repetitions of the bit data items of “1” or “0” from the held content.    
   
   
       4 . The random number test circuit according to  claim 3 , wherein the determination circuit includes a signal selection circuit which receives a signal indicating the held content.  
   
   
       5 . The random number test circuit according to  claim 3 , wherein the determination circuit includes an adder circuit which sums a plurality of values in the held content.  
   
   
       6 . The random number test circuit according to  claim 3 , wherein the determination circuit includes a counter circuit which counts a plurality of values in the held content.  
   
   
       7 . A random number generation circuit comprising: 
 a generation unit configured to generate the random number sequence; and    the random number test circuit according to  claim 3 , which tests the random number sequence.    
   
   
       8 . A random number test circuit comprising: 
 a receiving unit configured to receive a random number sequence;    a detection circuit configured to detect a plurality of bit data items of “1” and “0” in the random number sequence;    a plurality of shift registers which hold in series the bit data items of “1” and “0” repeated in the random number sequence, based on the detected bit data items;    a register which holds, based on the detected bit data items, a plurality of contents of the shift registers when the bit data items are switched from “1” and “0” to “0” and “1”, respectively; and    a determination circuit configured to determine types of repetitions of the bit data items “1” and “0” from the held contents.    
   
   
       9 . The random number test circuit according to  claim 8 , wherein the determination circuit includes a signal selection circuit which receives a plurality of signals indicating the held contents.  
   
   
       10 . The random number test circuit according to  claim 8 , wherein the determination circuit includes an adder circuit which sums a plurality of values in each of the held contents.  
   
   
       11 . The random number test circuit according to  claim 8 , wherein the determination circuit includes a counter circuit which counts a plurality of values in each of the held contents.  
   
   
       12 . A random number generation circuit comprising: 
 a generation unit configured to generate the random number sequence; and    the random number test circuit according to  claim 8 , which tests the random number sequence.    
   
   
       13 . A semiconductor integrated circuit device comprising: 
 a generation unit configured to generate a random number sequence;    a random number test circuit which tests the random number sequence supplied from the generation unit, and generates a test signal; and    an output terminal which outputs the test signal;    wherein the random number test circuit includes:    a receiving unit configured to receive the random number sequence;    a detection circuit configured to detect a plurality of bit data items of “1” and “0” in the random number sequence;    a plurality of shift registers which hold in series the bit data items of “1” and “0” repeated in the random number sequence, based on the detected bit data items;    a register which holds, based on the detected bit data items, a plurality of contents of the shift registers when the bit data items are switched from “1” and “0” to “0” and “1”, respectively; and    a determination circuit configured to determine types of repetitions of the bit data items “1” and “0” from the held contents.    
   
   
       14 . An integrated circuit card provided with a semiconductor integrated circuit, the semiconductor integrated circuit comprising: 
 a generation unit configured to generate a random number sequence;    a random number test circuit which tests the random number sequence supplied from the generation unit, and generates a test signal; and    an output terminal which outputs the test signal;    wherein the random number test circuit includes:    a receiving unit configured to receive the random number sequence;    a detection circuit configured to detect a plurality of bit data items of “1” and “0” in the random number sequence;    a plurality of shift registers which hold in series the bit data items of “1” and “0” repeated in the random number sequence, based on the detected bit data items;    a register which holds, based on the detected bit data items, a plurality of contents of the shift registers when the bit data items are switched from “1” and “0” to “0” and “1”, respectively; and    a determination circuit configured to determine types of repetitions of the bit data items “1” and “0” from the held contents.    
   
   
       15 . An information terminal device provided with a semiconductor integrated circuit, the semiconductor integrated circuit comprising: 
 a generation unit configured to generate a random number sequence;    a random number test circuit which tests the random number sequence supplied from the generation unit, and generates a test signal; and    an output terminal which outputs the test signal;    wherein the random number test circuit includes:    a receiving unit configured to receive the random number sequence;    a detection circuit configured to detect a plurality of bit data items of “1” and “0” in the random number sequence;    a plurality of shift registers which hold in series the bit data items of “1” and “0” repeated in the random number sequence, based on the detected bit data items;    a register which holds, based on the detected bit data items, a plurality of contents of the shift registers when the bit data items are switched from “1” and “0” to “0” and “1”, respectively; and    a determination circuit configured to determine types of repetitions of the bit data items “1” and “0” from the held contents.