Semiconductor device and manufacturing method thereof

Abstract

A method of manufacturing a semiconductor device is provided. First, a well region is formed in a substrate and then a mask layer is formed over the substrate. The mask layer and the substrate are patterned to form a first opening in the substrate. Thereafter, a threshold voltage adjustment process is performed. A gate dielectric layer, a first conductive layer and a second conductive layer are sequentially formed inside the first opening. The second conductive layer completely fills the first opening. A portion of the first conductive layer and the second conductive layer are removed so that the upper surface of the first conductive layer and the second conductive layer is slightly below the upper surface of the substrate and hence forms a second opening. A cap layer is formed in second opening and then the mask layer is removed. A source/drain region is formed in the substrate on each side of the first conductive layer. An inter-layer dielectric layer is formed over the substrate. Finally, using the cap layer as a self-aligned mask, a contact opening is formed in the inter-layer dielectric layer.

1 . A semiconductor device, comprising: 
 a substrate having an opening therein;    a dielectric layer formed on the interior surface of the opening;    a first conductive layer formed on the dielectric layer inside the opening;    a second conductive layer formed over the first conductive layer and filled the opening entirely;    a cap layer formed over the first conductive layer and the second conductive layer; and    a source/drain region formed in the substrate on each side of the second conductive layer.    
   
   
       2 . The semiconductor device of  claim 1 , wherein the first conductive layer has a U-shaped cross-sectional profile.  
   
   
       3 . The semiconductor device of  claim 1 , wherein the second conductive layer comprises a refractory metallic silicide layer.  
   
   
       4 . The semiconductor device of  claim 1 , wherein the first conductive layer comprises a doped polysilicon layer.  
   
   
       5 . The semiconductor device of  claim 1 , wherein the junction of the source/drain region is set at a level higher than a bottom of the opening.  
   
   
       6 . The semiconductor device of  claim 1 , wherein the junction of the source/drain region is set at a level slightly lower than a bottom of the opening.  
   
   
       7 . The semiconductor device of  claim 1 , wherein the device furthermore comprises a well region in the substrate.  
   
   
       8 . The semiconductor device of  claim 1 , wherein the junction of the source/drain region is at a level higher than a bottom of the polycide gate structure.  
   
   
       9 . The semiconductor device of  claim 1 , wherein the junction of the source/drain region is at a level slightly lower than a bottom of the polycide gate structure.