Adaptive reference voltage method and system

Abstract

An adaptive reference voltage method and system analyzes a received bus signal to evaluate voltage swing characteristics and adjusts the reference voltage for reading the signal to a level that compensates for variations in margins between high and low signal switching values such as are introduced by noise. A bus input signal analyzer circuit incorporated in an integrated circuit analyzes the bus signal received at the integrated circuit to adjust the reference voltage used by the integrated circuit. In one embodiment, the bus input signal analyzer circuit applies a feedback loop to adapt the reference voltage by setting high and low input values to a reference voltage generation circuit with the reference voltage centered between the high and low values, such as results from a resistor divider network.

1 - 14 . (canceled)  
   
   
       15 . An information handling system comprising: 
 plural integrated circuits operable to process information;    at least one bus interfacing at least a first and second of the plural integrated circuits, the bus operable to communicate information from the first integrated circuit to the second integrated circuit, the information communicated as at least one signal having high or low values, the second integrated circuit determining the signal value as high or low by comparing the signal value to a reference value; and    a bus signal analyzer associated with the second integrated circuit and operable to analyze the quality of the signal and to adjust the reference value to adapt to variations in signal quality.    
   
   
       16 . The information handling system of  claim 15  further comprising a reference voltage generator interfaced with the bus signal analyzer and operable to generate the reference value from a high value input and a low value input, the bus signal analyzer adjusting the reference value by adjusting the high and low value inputs.  
   
   
       17 . The information handling system of  claim 16  wherein the reference voltage generator comprises a resistor divider network.  
   
   
       18 . The information handling system of  claim 16  wherein the bus signal analyzer analyzes the quality of the signal by comparing the reference value, high value and low value with the bus signal value.  
   
   
       19 . The information handling system of  claim 19  wherein bus signal analyzer adjusts the high and low value inputs substantially equalize high and low noise margins associated with the bus signal.  
   
   
       20 . The information handling system of  claim 15  wherein the bus signal analyzer is integrated within the second integrated circuit.  
   
   
       21 . An information handling system comprising: 
 plural integrated circuits operable to process information;    a bus interfacing first and second of the plural integrated circuits, the bus communicating information with high and low voltage signals relative to a reference voltage signal; and    a bus signal analyzer operable to:    analyze the bus signal communicated between the first and second integrated circuits to evaluate bus signal noise; and    apply the bus signal noise analysis as feedback to dynamically adjust the reference voltage signal to a level that compensates for the bus signal noise.    
   
   
       22 . The information handling system of  claim 21  wherein: 
 analyzing the bus signal further comprises comparing the bus signal voltage swing characteristics with expected bus signal voltage swing characteristics to determine high and low voltage signal values associated with the bus signal; and    applying the bus signal noise analysis as feedback to dynamically adjust the reference voltage signal comprises setting the reference signal between the high and low voltage signals to substantially equalize high and low noise margins.    
   
   
       23 . The information handling system of  claim 22  further comprising: 
 a resistor divider network operable to set the reference voltage;    wherein the bus signal analyzer is further operable to input the high and low voltage signals into the resistor divider network to dynamically adjust the reference voltage.    
   
   
       24 . The information handling system of  claim 22  wherein determining the high and low voltage signal values further comprises: 
 adjusting a high voltage reference signal by a first offset associated with signal noise; and    adjusting a low voltage reference signal by a second offset associated with signal noise.    
   
   
       25 . The information handling system of  claim 21  wherein the bus signal analyzer comprises circuitry incorporated in one of the first and second integrated circuits.  
   
   
       26 . The information handling system of  claim 21  wherein the bus signal analyzer comprises circuitry incorporated in an information handling system motherboard.