Signal detector

Abstract

This invention includes a Clock Signal Detector and a Data Signal Detector. The Clock Signal Detector is designed to utilize a combination of a signal converter, rectifying-filtering circuit, and an inverter to prevent undetected signal interruption. With which, when a Clock signal interruption occurs that causes the signal converter and rectifying-filtering circuit unable to output clock and D.C. potential signals correspondingly, the inverter outputs a high potential signal as a warning for the detected abnormality in the clock signals. Through this warning, this signal detector can effectively prevent undetected interruptions during clock signal transmission through fiber optics or other wires, and, as a result, avoid time and resource wastages. The Data Signal Detector is designed to utilize a set of devices containing a signal converter, an integral charger, and an inverter. When the data ratio of positive potential signal in data signal transmission becomes overly high, the signal converter and integral charger correspondingly output a higher ratio data signal and integral potential signal. Once the high ratio is detected, the inverter outputs a low-potential signal to signify the abnormality in data signal. During data transmission, a short circuit or other factors may cause a series of data signal to be continuously transmitted, which, in turn, causes the laser to continuously fire. Through the above-described mechanism, the signal detector is able to prevent such continuous data transmission and laser emission, and, in turn, reduce the power attenuation and malfunction to occur to the laser emitter. In summary, the main function of the signal detector is to instantly detect interruptions in clock signal or abnormal transmission in data signal, and with an interruption control circuit, the detector reacts by intercepting the emitting action of the laser.

1 . A clock signal detector which is designed to be used in telecommunication transmission systems, said clock signal detector comprising: 
 a signal converter, which converts coupled input differential clock signal into single output clock signal;    a rectifying-filtering circuit connected to the signal converter and converting clock signals outputted from the signal converter into DC potential signal output; and    an inverter connected to the rectifying-filtering circuit and outputting the D.C. potential signal from the rectifying-filtering circuit as a reversed potential signal; wherein interruptions in clock signal transmission are detected such that when the interruption occurs, the signal converter and rectifying-filtering circuit cease to correspondingly output clock signal and D.C. potential signal; and wherein, once this is detected, the inverter outputs a high-potential signal, that is, a clock signal transmission abnormality detection potential signal.    
   
   
       2 . The clock signal detector as defined in  claim 1 , wherein said the signal converter serves to convert Low-Voltage Positive Emitter Coupling Logic (LVPECL) signal (input end) into Low-Voltage Transistor-Transistor Logic (LVTTL) signal (output end).  
   
   
       3 . The clock signal detector as defined in  claim 1 , wherein said rectifying-filtering circuit is comprised of a stand-alone rectifying component (i.e. micro inductor)  
   
   
       4 . The clock signal detector as defined in  claim 1 , wherein said inverter is comprised of a transistor circuit, at an input end, the regularly present D.C. potential signal being inputted into the base of the transistor, which connects the circuit between the collector and emitter of the transistor, and, regularly outputs a low potential from the output end at the collector; and wherein, when the clock signal disappears, the circuit closes the conduction between the collector and emitter of the transistor to trigger a high-potential output from the output end at the collector of the transistor; and wherein the effect of inversion is achieved, and the signal outputted is the so-called clock signal transmission abnormality detection potential signal.  
   
   
       5 . The clock signal detector as defined in  claim 1 , wherein said output end can be connected to an interruption control circuit at the emission end of a transmission system (i.e. laser emitter of the fiber-optic transmitter); and wherein a potential signal of clock signal transmission abnormality detection is used to drive the interruption control circuit to stop the signals from being continuously emitted.  
   
   
       6 . A data signal detector which is designed to be used in telecommunication transmission systems said data signal detector comprising: 
 a signal converter converting coupled input differential data signal into single output data signal;    an Integral Charger connected to the signal converter and converting the data signal inputted from the signal converter into a pulse type integral potential signal outputs wherein the potential signal approximately corresponds to a constant ratio of positive potential signal pulse; and    an inverter connected to the integral charger and outputting a D.C. potential signal from the integral charger as a reversed potential signal; wherein the data signal detector is capable of detecting overly high data ratio of data signals; and wherein, when the data ratio of positive potential signal in the differential data signal transmission becomes overly high, the signal converter and integral charger correspondingly output a higher ratio data signal and integral potential signal, and when the output surpassed the defined potential level, the inverter outputs a low-potential signal, that is, the data signal transmission abnormality detection potential signal.    
   
   
       7 . The data signal detector as defined in  claim 6 , the signal converter serves to convert Low-Voltage Positive Emitter Coupling Logic (LVPECL) signal (input end) into Low-Voltage Transistor-Transistor Logic (LVTTL) signal (output end).  
   
   
       8 . The data signal detector as defined in  claim 6 , the second resister of the integral charger can be connected to the capacitor in parallel, which is then connected to the first resister with a tandem connection; wherein the first resistor is the input end and the tandem connection point between the first resistor and the second resistor is the output end and another end of the second resistor is grounded; and wherein threshold voltage output potential is Vb and the charge formula is Vb=Va*VR*[1−e(−t/TC)]+Vinitial e raise the power of (−t/TC), in which,  
         TC=R   1 * R   2 * C   2 /( R   1 + R   2 )    VR=R   2 /( R   1 + R   2 )    Vinitial=Va*VR/ 2  
   
   
       9 . The data signal detector as defined in  claim 6 , this inverter serves as a Logic Gate and makes logic decisions to the inputted integral potential signal, enabling while input of a constant ratio of integral potential pulses and reverses the potential pulses into a high potential signal for output, wherein the data ratio of positive potential signal in the differential data signal transmission becomes overly high, hen being inputted as a higher ratio integral signal pulse and reversed into a low-potential signal for output; and wherein this mechanism, reversion is achieved, and the outputted signal is the so-called data signal transmission abnormality detection potential signal.  
   
   
       10 . The data signal detector as defined in  claim 6 , the output end can be connected to an interruption control circuit at the emission end of a transmission system (i.e. laser emitter of the fiber-optic transmitter end), and wherein potential signal of data signal transmission abnormality detection is used to drive the interruption control circuit to stop the signals from being continuously emitted.  
   
   
       11 . A signal detector, which is designed to be used in telecommunication transmission systems, said signal detector comprising: 
 a signal converter converting coupled input differential data signal into single output data signal;    a clock signal detector receiving converted single output clock signals; wherein, when this single output clock signal is in a normal state, the clock signal detector outputs a low-potential clock detection signal, and when this single output clock signal is interrupted, the system outputs a high-potential clock detection signal;    a data signal detector receiving converted single output data signals; wherein, when this single output data signal is in a normal state, the data signal detector outputs a low-potential data detection signal, and when this single output data signal is in an abnormal state and outputs positive potential continuously, the system outputs a high-potential data detection signal; and an interruption control circuit receiving converted clock and data signals and determining production of control signals according to the potential states of the clock and data detection signals; wherein, through the control signal, the interruption control circuit controls whether to emit transmission signals at the emission end of the transmission system.    
   
   
       12 . The signal detector as defined in  claim 11 , the signal detector comprising: 
 a signal converter converting coupled input differential clock signal into single output clock signal;    a rectifying-filtering circuit connected to the signal converter and converting clock signals outputted from the signal converter into DC potential signal output; and    an inverter is connected to the rectifying-filtering circuit and outputting a D.C. potential signal from the rectifying-filtering circuit as a reversed potential signal; wherein the clock signal detector detects interruptions in clock signal transmission; wherein when the interruption occurs, the signal converter and rectifying-filtering circuit cease to correspondingly output clock signal and D.C. potential signal; and wherein, once detected, the inverter outputs a high-potential signal, that is, a clock signal transmission abnormality detection potential signal.    
   
   
       13 . The signal detector as defined in  claim 11 , wherein the signal detector comprising: 
 a signal converter converting coupled input differential data signal into single output data signal;    an Integral Charge connected to the signal converter and converting the data signal inputted from the signal converter into a pulse type integral potential signal output; wherein the potential signal approximately corresponds to a constant ratio of positive potential signal pulse; and    an inverter connected to the integral charger and outputting a D.C. potential signal from the integral charger as a reversed potential signal wherein the data signal detector is capable of detecting overly high data ratio of data signal; and wherein when the data ratio of positive potential signal in the differential data signal transmission becomes overly high, the signal converter and integral charger correspondingly output a higher ratio data signal and integral potential signal, and when the output surpassed the defined potential level, the inverter outputs a low-potential signal, that is, the data signal transmission abnormality detection potential signal.    
   
   
       14 . The signal detector as defined in  claim 11 , the output end of the clock signal detector and data signal detector can be individually connected to the interruption control circuit at the emission ends of the transmission system (i.e. laser emitter of the fiber-optic transmitter) and wherein the potential signal of data signal transmission abnormality detection, in conjunction with the potential signal of clock signal abnormality detection, is used to drive the interruption control circuit to stop the signals from being continuously emitted.  
   
   
       15 . The signal detector as defined in  claim 11 , the potential states of clock and data detection signals, as described in the interruption control circuit section, refer to the positive potential control signals used to interrupt signal emission from the emitting end of the transmission system when an interruption in clock signal or abnormal continuous transmission of data signal occur; contrariwise, the control signal will not be produced.  
   
   
       16 . The signal detector as defined in  claim 11 , wherein the second resister of the integral charger can be connected to the capacitor in parallel, which is then connected to the first resister with a tandem connection; wherein the first resistor is the input end and the tandem connection point between the first resistor and the second resistor is the output end, wherein another end of the second resistor is grounded, and wherein threshold voltage output potential is Vb and the charge formula is Vb=Va*VR*[1−e(−t/TC)]+Vinitial e raise the power of (−t/TC) in which,  
         TC=R   1 * R   2 * C   2 /( R   1 + R   2 )    VR=R   2 /( R   1 + R   2 )    Vinitial=Va*VR/ 2