Circuit for programming antifuse bits

Abstract

Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the speed at which antifuse elements may be programmed. In one embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current through the antifuse element once it is programmed. In another embodiment, circuitry is provided for generating a separate programming pulse for each antifuse element, which is selected for programming.

1 . An integrated circuit memory product comprising: 
 at least one bank of antifuse elements in which the top plates of the antifuse elements are joined in a common connection to a programming voltage;    a selection transistor in series with each antifuse element in the bank, the enablement of a particular selection transistor resulting in a path being provided for the programming of the antifuse element associated with the enabled selection transistor; and    a feedback circuit associated with each antifuse element in the bank to stop the flow of current through its associated antifuse element once the antifuse element is programmed.    
   
   
       2 . The apparatus of  claim 1  further comprising circuitry for verifying that antifuse elements have been programmed correctly and that unprogrammed antifuse elements are functioning properly.  
   
   
       3 . The apparatus of  claim 2 , wherein the verification circuitry includes: 
 circuitry for connecting the antifuse element in series with a node;    circuitry including a transistor that is sufficient to charge the voltage at the node from a first voltage to a second voltage; and    circuitry for detecting whether (a) the node is charged to the second voltage or (b) has remained at the first voltage which indicates that an unprogrammed antifuse is leaky.    
   
   
       4 . The apparatus of  claim 2 , wherein the verification circuitry includes: 
 circuitry for connecting the antifuse element in series with a node;    circuitry including a parallel combination of a first transistor and a second transistor that is sufficient to charge the node from a first voltage to a second voltage; and    circuitry for detecting whether (a) the node is charged to the second voltage or (b) the node remains at the first voltage thereby indicating that the antifuse element is programmed properly.    
   
   
       5 . An integrated circuit memory product comprising: 
 a plurality of banks of antifuse elements, each bank including a plurality of antifuse elements;    circuitry for selecting one of the banks of antifuse elements for programming; and    circuitry for providing a separate programming pulse to each of the antifuse elements in the selected bank that is to be programmed.    
   
   
       6 . The apparatus of  claim 1  further comprising circuitry for verifying that antifuse elements have been programmed correctly and that unprogrammed antifuse elements are functioning properly.  
   
   
       7 . The apparatus of  claim 2 , wherein the verification circuitry includes: 
 circuitry for connecting the antifuse element in series with a node;    circuitry including a transistor that is sufficient to charge the voltage at the node from a first voltage to a second voltage; and    circuitry for detecting whether (a) the node is charged to the second voltage; or (b) has remained at the first voltage which indicates that an unprogrammed antifuse is leaky.    
   
   
       8 . The apparatus of  claim 2 , wherein the verification circuitry includes: 
 circuitry for connecting the antifuse element in series with a node;    circuitry including a parallel combination of a first transistor that is sufficient to charge the node from a first voltage to a second voltage; and    circuitry for detecting whether (a) the node is charged to the second voltage or (b) has remained at the first voltage thereby indicating that the antifuse element is programmed properly.    
   
   
       9 . A method of verifying antifuses in a semiconductor memory, comprising: 
 connecting the antifuse in series with a node;    providing current to the node which is sufficient to charge the node from a first to a second voltage; and    detecting whether (a) the node charges to the second voltage; or (b) remains at the first voltage thereby indicating that the antifuse is leaky.    
   
   
       10 . The method of  claim 9 , further comprising: 
 providing charging current to the node through the parallel combination of a first transistor and a second transistor, which current is sufficient to charge the node from a first voltage to a second voltage; and    detecting whether the voltage at the node (a) charges to the second voltage; or (b) remains at the second voltage which indicates that the antifuse is properly programmed.