Conductive through wafer vias

Abstract

Methods for fabricating a conductive contact (through-via) through a full thickness of a substrate such as a semiconductor wafer or interposer substrate, and semiconductor devices and systems incorporating the conductive through-via are provided. The conductive contact is fabricated by applying a metal layer onto a backside of a substrate, forming a through-hole through the substrate and the metal layer, sealing the hole in the metal layer by an electroless plating process, and filling the hole by an electroplating or an electroless plating process.

1 . A semiconductor device, comprising: a substrate comprising first and second surfaces, a layer of a metal over the first surface of the substrate, and an opening extending through the substrate and the metal layer, the opening in the metal layer having a radius, and the metal layer having a thickness of about one-tenth of said radius of the opening.  
   
   
       2 . The device of  claim 1 , wherein the thickness of the metal layer is about 0.2 μm to about 2 μm.  
   
   
       3 . The device of  claim 1 , wherein the metal layer over the first surface of the substrate comprises a plated metal layer.  
   
   
       4 . The device of  claim 1 , wherein the metal layer comprises a metal foil adhered to the first surface of the substrate.  
   
   
       5 . The device of  claim 1 , wherein the substrate comprises a semiconductive material selected from the group consisting of monocrystalline silicon, polycrystalline silicon, germanium, silicon-on-glass, and silicon-on-sapphire.  
   
   
       6 . The device of  claim 1 , wherein the substrate comprises a semiconductor wafer.  
   
   
       7 . The device of  claim 1 , wherein the substrate comprises a non-conductive material selected from the group consisting of ceramic, polymer resin, glass-filled epoxy resin, and aramid-filled resin.  
   
   
       8 . A semiconductor device, comprising: a substrate comprising first and second surfaces, a layer of a metal over the first surface of the substrate, and an opening extending through the substrate and the metal layer, the opening having sidewalls defined by the substrate and an isolation layer on said sidewalls, the opening through the metal layer having a radius and sidewalls defined by the substrate, and the metal layer having a thickness of about one-tenth of said radius of the opening.  
   
   
       9 . The device of  claim 8 , wherein the isolation layer comprises a material selected from the group consisting of oxide, nitride, oxynitride, and glass.  
   
   
       10 . The device of  claim 8 , wherein the isolation layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride.  
   
   
       11 . The device of  claim 8 , wherein the isolation layer comprises a glass selected from the group consisting of borophosphosilicate glass, phosphosilicate glass, and borosilicate glass.  
   
   
       12 . The device of  claim 8 , wherein the isolation layer comprises an insulating polymeric material.  
   
   
       13 . The device of  claim 12 , wherein the polymeric material is selected from the group consisting of bismaleimide triazine (BT) resin, benzocyclobutene, polybenzoxazole, and polyimide.  
   
   
       14 . A semiconductor device, comprising: a nonconductive substrate comprising first and second surfaces, a layer of a metal over the first surface of the substrate, and an opening extending through the substrate and the metal layer, the opening in the metal layer having a radius, and the metal layer having a thickness of about one-tenth of said radius of the opening.  
   
   
       15 . The device of  claim 14 , wherein the substrate comprises a material selected from the group consisting of ceramic, polymer resin, glass-filled epoxy resin, and aramid-filled resin.  
   
   
       16 . A semiconductor device, comprising: a substrate comprising first and second surfaces, a layer of a metal over the first surface of the substrate, an opening extending through the substrate and the metal layer, and a plated metal plug sealing the opening of the metal layer.  
   
   
       17 . A semiconductor device, comprising: a substrate comprising first and second surfaces, a layer of a metal over the first surface of the substrate, an opening extending through the substrate and the metal layer, the opening having sidewalls defined by the substrate and an isolation layer on said sidewalls, and a plated metal plug sealing the opening of the metal layer.  
   
   
       18 . A semiconductor device, comprising: a substrate comprising first and second surfaces, a layer of a metal over the first surface of the substrate, an opening extending through the substrate and the metal layer, a plated metal plug sealing the opening of the metal layer, and a plated metal fill overlying the plated metal plug within the opening in the substrate.  
   
   
       19 . A semiconductor device, comprising: a substrate comprising first and second surfaces, a layer of a metal over the first surface of the substrate, an opening extending through the substrate and the metal layer, the opening having sidewalls defined by the substrate and an isolation layer on said sidewalls, a plated metal plug sealing the opening of the metal layer, and a plated metal fill overlying the plated metal plug within the opening in the substrate.  
   
   
       20 . A semiconductor wafer, comprising first and second surfaces, and a thickness, a layer of a metal over the first surface of the wafer, and an opening extending through the thickness of the wafer and the metal layer, the opening in the metal layer having a radius, and the metal layer having a thickness of about one-tenth of said radius of the opening.  
   
   
       21 . A semiconductor wafer, comprising first and second surfaces, and a thickness, a layer of a metal over the first surface of the wafer, and an opening extending through the thickness of the wafer and the metal layer, the opening having sidewalls defined by the substrate and an isolation layer on said sidewalls, the opening in the metal layer having a radius, and the metal layer having a thickness of about one-tenth of said radius of the opening.  
   
   
       22 . A semiconductor wafer, comprising first and second surfaces, and a thickness, a layer of a metal over the first surface of the wafer, and an opening extending through the thickness of the wafer and the metal layer, and a plated metal plug sealing the opening of the metal layer.  
   
   
       23 . A semiconductor wafer, comprising: first and second surfaces, a layer of a metal on the first surface of the wafer, an opening extending through the wafer and the metal layer, the opening defined by sidewalls of the wafer, an isolation layer over said sidewalls within the opening, a conductive contact within the opening comprising a plated metal plug sealing the opening through the metal layer and a plated metal filling the opening through the wafer.  
   
   
       24 . A semiconductor wafer, comprising: first and second surfaces, a layer of a metal on the first surface of the wafer, an opening extending through the wafer and the metal layer, the opening defined by sidewalls of the wafer, an isolation layer over said sidewalls within the opening, a conductive contact within the opening comprising an electrolessly plated metal plug sealing the opening through the metal layer and an electroplated metal filling the opening through the wafer.  
   
   
       25 . A semiconductor wafer, comprising: first and second surfaces, a layer of a metal on the first surface of the wafer, an opening extending through the wafer and the metal layer, the opening defined by sidewalls of the wafer, an isolation layer over said sidewalls within the opening, a conductive contact within the opening comprising a plated metal plug sealing the opening through the metal layer and a plated metal filling the opening through the wafer. the metal layer patterned to define a circuit trace extending from the conductive contact to a contact pad on the first surface of the wafer.  
   
   
       26 . An interposer for a semiconductor device, comprising: a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, a plated metal plug sealing the opening through the metal layer and a plated metal filling the opening through the substrate.  
   
   
       27 . The interposer of  claim 26 , wherein the plated metal filling the via within the wafer comprises an electrolessly plated metal.  
   
   
       28 . The interposer of  claim 26 , wherein the plated metal filling the via within the wafer comprises an electroplated metal.  
   
   
       29 . The interposer of  claim 26 , wherein the substrate comprises a semiconductive material.  
   
   
       30 . The interposer of  claim 26 , wherein the substrate comprises an electrically insulating material.  
   
   
       31 . An interposer for a semiconductor device, comprising: a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, an isolation layer over sidewalls of the substrate within the opening, a plated metal plug sealing the opening through the metal layer, and a plated metal over the isolation layer and filling the opening through the substrate.  
   
   
       32 . An interposer for a semiconductor device, comprising: a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, an isolation layer over sidewalls of the substrate within the opening, an electrolessly plated metal plug sealing the opening through the metal layer, and a plated metal over the isolation layer and filling the opening through the substrate.  
   
   
       33 . An interposer for a semiconductor device, comprising: a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, an isolation layer over sidewalls of the substrate within the opening, a plated metal plug sealing the opening through the metal layer, a plated metal over the isolation layer and filling the opening through the substrate, and the metal layer patterned to define a circuit trace extending from the plated metal plug to a contact pad on the first surface of the wafer.  
   
   
       34 . A semiconductor device comprising the interposer of  claim 33 .  
   
   
       35 . An interposer for an electrical component, comprising: a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, a conductive contact filling the opening and comprising a plated metal plug sealing the opening through the metal layer and a plated metal fill within the opening through the substrate, the conductive contact in electrical communication with a contact pad on each of the first and second surfaces of the substrate.  
   
   
       36 . The interposer of  claim 35 , wherein at least one of the first and second surfaces of the substrate of the interposer comprise a plurality of contact pads arranged in a pattern corresponding to contact pads on the electrical component to be connected thereto.  
   
   
       37 . The interposer of  claim 35 , wherein at least one of the first and second surfaces of the substrate of the interposer comprise a plurality of contact pads arranged in a pattern different than a pattern of bond pads on the electrical component to be connected thereto to provide rerouting of said bond pads.  
   
   
       38 . An interposer for an electrical component, comprising: a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, a conductive contact filling the opening and comprising a plated metal plug sealing the opening through the metal layer and a plated metal fill within the opening through the substrate, a contact pad on each of the first and second surfaces of the substrate, the conductive contact in electrical communication with the contact pads wherein the metal layer is patterned to define a circuit trace extending from the conductive contact to the contact pad on the first surface of the substrate.  
   
   
       39 . An assembly comprising an electrical component mounted on an interposer, the interposer comprising: 
 a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, a conductive contact filling the opening and comprising a plated metal plug sealing the opening through the metal layer and a plated metal fill within the opening through the substrate, the conductive contact in electrical communication with a contact pad on each of the first and second surfaces of the substrate.    
   
   
       40 . An assembly comprising an electrical component mounted on an interposer, the interposer comprising: 
 a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, a conductive contact filling the opening and comprising a plated metal plug sealing the opening through the metal layer and a plated metal fill within the opening through the substrate, a plurality of contact pads on each of the first and second surfaces of the substrate, the conductive contact in electrical communication with at least one of said contact pads on each of the first and second surfaces of the substrate.    
   
   
       41 . The assembly of  claim 40 , wherein the plurality of contact pads on the surface of the substrate of the interposer which the electrical component is mounted thereon are arranged in a pattern corresponding to contact pads of the electrical component.  
   
   
       42 . The assembly of  claim 40 , wherein the plurality of contact pads on the surface of the substrate of the interposer which the electrical component is mounted thereon are arranged in a pattern different than a pattern of bond pads of the electrical component to provide rerouting of said bond pads.  
   
   
       43 . The assembly of  claim 40 , wherein the electrical component is selected from the group consisting of a flip chip and a die package.  
   
   
       44 . The assembly of  claim 40 , wherein the electrical component is selected from the group consisting of a test substrate, a higher level carrier substrate, a memory device, and a circuit board.  
   
   
       45 . The assembly of  claim 44 , wherein the electrical component comprises a probe card for testing a semiconductor die.  
   
   
       46 . An assembly comprising a semiconductor die mounted on an interposer, the interposer comprising: 
 a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, a conductive contact filling the opening and comprising an electrolessly plated metal plug sealing the opening through the metal layer and an electroplated plated metal fill within the opening through the substrate, and a plurality of contact pads on each of the first and second surfaces of the substrate, the conductive contact in electrical connection with at least one of said contact pads situated on the surface of the interposer substrate onto which the semiconductor die is mounted, and said contact pad on the interposer substrate in electrical communication with a contact pad of the semiconductor die.    
   
   
       47 . An assembly comprising first and second electrical components mounted on an interposer, the interposer comprising: 
 a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, a conductive contact filling the opening and comprising an electrolessly plated metal plug sealing the opening through the metal layer and an electroplated plated metal fill within the opening through the substrate, and a plurality of contact pads on each of the first and second surfaces of the interposer substrate, the conductive contact in electrical connection with at least one contact pad situated on each of the first and second surfaces of the interposer substrate, wherein the first and second electrical components are mounted, respectively, on the first and second surfaces of the interposer substrate, and each of the first and second electrical components have a contact pad in electrical connection to said contact pad situated, respectively, on the first surface and on the second surface of the interposer substrate.    
   
   
       48 . The assembly of  claim 47 , wherein one of the electrical components is selected from the group consisting of a flip chip and a die package, and another of the electrical components is selected from the group consisting of a test substrate, a higher level carrier substrate, a memory device, and a circuit board.  
   
   
       49 . A system, comprising: 
 a microprocessor; and    a memory device in communication with the microprocessor, the memory device comprising a device according to  claim 1 .    
   
   
       50 . A system, comprising: 
 a microprocessor; and    a memory device in communication with the microprocessor, the memory device comprising an interposer according to  claim 27 .    
   
   
       51 . A system, comprising: 
 a microprocessor; and    a memory device in communication with the microprocessor, the memory device comprising an interposer according to  claim 35.