Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein

Abstract

A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

1 . A micro-controller for performing a process in accordance with a program, comprising: 
 two dictionary memories for storing instruction codes which appear in the program;    a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program, each said compressed code having a word length sufficiently long to identify all instruction codes included in the program, each said compressed code having a value indicative of an address in said dictionary memory at which an associated instruction code is stored; and    reading means for simultaneously reading two consecutive compressed codes every other clock and temporarily storing the two compressed codes in registers, respectively,    responsive to an instruction code read request which specifies an address of a compressed code, to read two consecutive compressed codes stored in the specified address in said compressed code memory, and to store the read compressed codes in said registers,    responsive to the compressed codes which respectively indicate different dictionary memories to simultaneously read instruction codes stored at addresses indicated by the respective compressed codes, and to output the instruction codes in an order of the consecutive compressed codes associated therewith, and    responsive to the compressed codes which respectively indicate the same dictionary memory to read instruction codes stored at addresses indicated by the compressed codes in an order of the consecutive compressed codes, and to output the instruction codes.