US2005196960A1PendingUtilityA1
Method of forming metal silicide film and method of manufacturing semiconductor device having metal silicide film
Priority: Oct 17, 2002Filed: Apr 26, 2005Published: Sep 8, 2005
Est. expiryOct 17, 2022(expired)· nominal 20-yr term from priority
H10D 64/0131H10D 30/0212C23C 14/5806C23C 14/5873C23C 14/165C23C 14/021
37
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Claims
Abstract
A metal-containing film is formed on a silicon-containing conductive region at a temperature where the metal of the metal-containing film and silicon of the semiconductor substrate react with each other to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the and the semiconductor substrate. The resultant structure is annealed so that metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form a metal silicide film.
Claims
exact text as granted — not AI-modified1 . A method of forming a metal silicide film, comprising:
forming a metal-containing film on a surface of a semiconductor substrate having an insulating region and a silicon-containing conductive region, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the silicon-containing conductive region; and annealing the resultant structure so that metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form the metal silicide film.
2 . The method of claim 1 , further comprising forming a titanium-rich capping film on the metal-containing film prior to the annealing.
3 . The method of claim 1 , wherein metal-containing film is at least one selected from the group consisting of TaN, NiTa, Ti, TiN, Ta, W, WN, Hf, Nb, Mo, RuO 2 , Mo 2 N, Ni, Ir, Pt, Cr, RuO, Mo 2 N, WNx, NiPt, or a combination thereof.
4 . The method of claim 2 , wherein the annealing, comprises:
a first annealing at a temperature range of 350 to 650° C.; removing the titanium-rich capping film; and a second annealing at a temperature range of 700-900° C.
5 . The method of claim 1 , wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate; and etching the semiconductor substrate by radio frequency (RF) sputtering.
6 . The method of claim 1 , wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate using a hydrogen fluoride (HF) solution diluted with deionized (DI) water; wet-cleaning the surface of the semiconductor substrate using a mixture solution of ammonium hydroxide, hydrogen peroxide (H 2 O 2 ), and water; and wet-cleaning the surface of the semiconductor substrate using a HF solution diluted with DI water.
7 . The method of claim 1 , wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate using a mixture solution of sulfuric acid and H 2 O 2 ; and wet-cleaning the surface of the semiconductor substrate using a HF solution diluted with DI water.
8 . The method of claim 1 , wherein the metal-containing film is formed at a temperature range of 300-500° C.
9 . A method of manufacturing a semiconductor device, said method comprising:
forming an isolation region defining an active region on a semiconductor substrate; forming on the active region a transistor having source/source regions and a gate; forming a metal-containing film on a surface of the semiconductor substrate, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the semiconductor substrate react with each other to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the and the semiconductor substrate; and annealing the resultant structure so that metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form the metal silicide film.
10 . The method of claim 9 , further comprising forming a titanium-rich capping film on the metal-containing film.
11 . The method of claim 9 , wherein forming of the metal-containing film comprises forming the metal-containing film exclusively on a surface of the gate, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the gate to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the gate.
12 . The method of claim 9 , wherein forming of the metal-containing film comprises forming the metal-containing film exclusively on a surface of the source/drain region, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the source/drain regions to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the source/drain region.
13 . The method of claim 9 , wherein forming of the metal-containing film comprises forming the metal-containing film on a surface of the source/drain region and the gate, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the source/drain regions and the gate to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the source/drain region and the gate.
14 . The method of claim 9 , wherein metal-containing film is at least one selected from the group consisting of TaN, NiTa, Ti, TiN, Ta, W, WN, Hf, Nb, Mo, RuO 2 , Mo 2 N, Ir, Pt, Cr, RuO, Mo 2 N, WNx, NiPt, or a combination thereof.
15 . The method of claim 10 , wherein the annealing, comprises:
a first annealing at a temperature range of 350 to 650° C.; removing the titanium-rich capping film; and a second annealing at a temperature range of 700-900° C.
17 . The method of claim 9 , wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate; and etching the semiconductor substrate by radio frequency (RF) sputtering.
18 . The method of claim 9 , wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate using a hydrogen fluoride (HF) solution diluted with deionized (DI) water; wet-cleaning the surface of the semiconductor substrate using a mixture solution of ammonium hydroxide, hydrogen peroxide (H 2 O 2 ), and water; and wet-cleaning the surface of the semiconductor substrate using a HF solution diluted with DI water.
19 . The method of claim 9 , wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate using a mixture solution of sulfuric acid and H 2 O 2 ; and wet-cleaning the surface of the semiconductor substrate using a HF solution diluted with DI water.
20 . The method of claim 9 , wherein the metal-containing film is formed at a temperature range of 300-500° C.Join the waitlist — get patent alerts
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