Mask layout and exposing method for reducing diffraction effects by using a single mask in the process of semiconductor production

Abstract

The present invention discloses appropriate layout design of a single mask and proper operation of exposing device in the process of semiconductor production for reducing diffraction effects caused by tiny pattern in exposing process, therefore effectively enhances the resolution in exposing process, and increases the yield.

1 . A mask layout for reducing diffraction effects in the process of semiconductor production of which being two sections divided on the same mask substrate, the first pattern section and the second pattern section having pattern that matches first pattern being deployed on said two sections for the patterns on said two sections to be able to exposed on one specific section within several times to reduce diffraction effects.  
     
     
         2 . The mask layout according to  claim 1 , wherein said two patterns with matching shape in said two sections on said mask can be any kind of matching pattern.  
     
     
         3 . The mask layout according to  claim 1 , wherein said two patterns with matching shape in said two sections on said mask can be transversely matching or longitudinally matching.  
     
     
         4 - 22 . (canceled)