US2005195662A1PendingUtilityA1

Non-volatile memory device conducting comparison operation

Assignee: MITSUBISHI ELECTRIC CORPPriority: Aug 22, 2002Filed: May 9, 2005Published: Sep 8, 2005
Est. expiryAug 22, 2022(expired)· nominal 20-yr term from priority
Inventors:Tsukasa Ooishi
G11C 11/1675G11C 2013/0076G11C 2013/0078G11C 13/0004G11C 15/04G11C 15/046G11C 13/0069G11C 29/028G11C 29/50G11C 2213/72G11C 11/15G11C 15/02G11C 11/16G11C 29/02G11C 2213/79G11C 29/026G11C 7/062G11C 2013/008G11C 2207/063
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Claims

Abstract

The non-volatile memory device includes a current detection circuit for comparing, in data retrieve operation, storage information written in a non-volatile manner in a memory cell row with retrieval information in order to determine whether or not the storage information matches the retrieval information. The current detection circuit compares a data read current flowing through each bit line corresponding to each memory cell of a memory cell row storing the storage information with a data read current flowing through each bit line corresponding to each retrieval memory cell storing the retrieval information.

Claims

exact text as granted — not AI-modified
1 . A non-volatile memory device, comprising: 
 a plurality of memory cells arranged in a matrix, and each having an electric resistance varying according to storage data written in a non-volatile manner by a data write current;    a plurality of word lines provided corresponding to memory cell rows respectively;    a plurality of bit lines provided corresponding to memory cell columns respectively; and    a control circuit for conducting one of data write operation and data read operation wherein    each of data write operation and data read operation is divided into a plurality of cycles, said control circuit conducts a part of said one of data write operation and data read operation in each of said cycles by pipeline processing.    
     
     
         2 . The non-volatile memory device according to  claim 1 , further comprising: 
 an address latch circuit for temporarily holding information for selecting a memory cell row and a memory cell column, wherein    said address latch circuit operates in synchronization with each of said plurality of cycles.    
     
     
         3 . The non-volatile memory device according to  claim 1 , further comprising: 
 a data latch circuit for temporarily holding data transmitted between a selected memory cell and a data output node, wherein    said data latch circuit operates in synchronization with each of said plurality of cycles.

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