Inspection condition setting program, inspection device and inspection system
Abstract
A program is provided for setting efficiently, and with precision, the inspection conditions of an inspection device that detects particles and deformed patterns in or on products such as semiconductor integrated circuits that are manufactured by simultaneously forming a plurality of products on a single substrate. In particular, the system achieves greater efficiency of the setting of cell comparison regions and the setting of non-inspection regions. Input processing of a product type code, input processing of chip size and configuration information, reading processing of circuit layout data, extraction processing of repeated pattern region coordinates, extraction processing of sparse region coordinates and circuit pattern condition registration processing are sequentially executed.
Claims
exact text as granted — not AI-modified1 . A program for setting inspection conditions that is executed for setting inspection conditions of an inspection device that detects the positions of particles or deformed patterns present in or on a subject of inspection, wherein the program executes:
circuit layout reading processing of reading circuit layout data formed on the subject of inspection; repeated pattern region coordinates extraction processing in which the coordinates of repeated pattern regions in the circuit layout are extracted from the circuit layout data that has thus been read in the circuit layout reading processing; and inspection region registration processing in which the coordinates of repeated pattern regions that have thus been extracted by the repeated pattern region coordinates extraction processing are registered as inspection regions of the inspection device.
2 . A program for setting inspection conditions that-is executed for setting inspection conditions of an inspection device that detects the position of particles or deformed patterns present in or on a subject of inspection, wherein the program executes:
circuit layout reading processing of reading circuit layout data formed on the subject of inspection; designated circuit block region coordinates extraction processing in which the coordinates of designated circuit block regions are extracted from the circuit layout data that has thus been read in the circuit layout reading processing; and inspection region registration processing in which the coordinates of circuit block regions that have thus been extracted by the designated circuit block region coordinates extraction processing are registered as inspection regions of the inspection device.
3 . A program for setting inspection conditions that is executed for setting inspection conditions of an inspection device that detects the position of particles or deformed patterns present in or on a subject of inspection, wherein the program executes:
circuit layout reading processing of reading circuit layout data formed on the subject of inspection; sparse region coordinates extraction processing in which the coordinates of regions where the circuit pattern is sparse are extracted from the circuit layout data that has thus been read in the circuit layout reading processing; and non-inspection region coordinates registration processing in which the coordinates of the sparse regions that have thus been extracted by the sparse region coordinates extraction processing are registered as non-inspection regions of the inspection device.
4 . The program for setting inspection conditions according to claim 1 wherein the circuit layout data that is read in said circuit layout reading processing is the output data of a CAD system.
5 . The program for setting inspection conditions according to claim 2 wherein the circuit layout data that is read in said circuit layout reading processing is the output data of a CAD system.
6 . The program for setting inspection conditions according to claim 3 wherein the circuit layout data that is read in said circuit layout reading processing is the output data of a CAD system.
7 . The program for setting inspection conditions according to claim 1 wherein array sections are extracted from the circuit layout data in said repeated pattern region coordinates extraction processing.
8 . The program for setting inspection conditions according to claim 1 wherein the same processing as in cell comparison inspection provided by the inspection device is executed with respect to the circuit layout data in said repeated pattern region coordinates extraction processing.
9 . The program for setting inspection conditions according to claim 3 wherein, in said sparse region coordinates extraction processing, the probability of occurrence of short-circuiting or disconnection is calculated with respect to the circuit layout data and the coordinates of regions where the probability of occurrence of short-circuiting or disconnection has a value smaller than the threshold value which is given beforehand are extracted.
10 . The program for setting inspection conditions according to claim 3 wherein, in said sparse region coordinates extraction processing, the density of the circuit patterns are calculated with respect to the circuit layout data and the coordinates of regions where the density is less than a previously given value are extracted.
11 . The program for setting inspection conditions according to claim 3 wherein, in said sparse region coordinates extraction processing, the coordinates of scribe line regions between one chip and another chip of the integrated circuits are extracted as sparse regions.
12 . The program for setting inspection conditions according to claim 1 wherein, in order to execute said repeated pattern region coordinates extraction processing and said inspection region coordinates registration processing, a graphical user interface is provided, and repeated pattern regions are output to this graphical user interface.
13 . The program for setting inspection conditions according to claim 2 wherein, in order to execute said designated circuit block region coordinates extraction processing and said inspection region coordinates registration processing, a graphical user interface is provided, and circuit block regions are output to this graphical user interface.
14 . The program for setting inspection conditions according to claim 3 wherein, in order to execute said sparse region coordinates extraction processing and said non-inspection region coordinates registration processing, a graphical user interface is provided, and sparse regions are output to this graphical user interface.
15 . An inspection device comprising:
a calculation unit that extracts the coordinates of repeated pattern regions in a circuit layout from circuit layout data formed on the subject of inspection; a storage unit that registers as inspection regions the coordinates of this extracted repeated pattern regions; and an inspection unit that reads this inspection regions that have been registered in the storage section and detects the position of particles or deformed patterns present in or on the inspection subject.
16 . An inspection system comprising:
an inspection device that detects the position of particles or deformed patterns present in or on a subject of inspection; and a device management unit comprising calculation means that extracts the coordinates of a repeated pattern regions in the circuit layout from circuit layout data formed on the subject of inspection, storage means that registers as inspection regions the coordinates of these extracted repeated pattern regions, and output means that provides these inspection regions registered in the storage means to this inspection device, which is connected through a network.
17 . An inspection device comprising:
a calculation unit that extracts the coordinates of a designated circuit block regions from circuit layout data formed on a subject of inspection; a storage unit that registers as an inspection region the coordinates of these extracted circuit block regions; and an inspection unit that reads these inspection regions registered in the storage section and detects the positions of particles or deformed patterns present in or on the subject of inspection.
18 . An inspection system comprising:
an inspection device that detects the positions of particles or deformed patterns present in or on a subject of inspection; and a device management unit comprising calculation means that extracts the coordinates of a designated circuit block regions from circuit layout data formed on the subject of inspection, storage means that registers as inspection regions the coordinates of this extracted circuit block regions, and output means that provides this inspection region registered in the storage means to this inspection device, which is connected through a network.
19 . An inspection device comprising:
a calculation unit that extracts the coordinates of regions where the circuit patterns are sparse from circuit layout data formed on a subject of inspection; a storage unit that registers as a non-inspection regions the coordinates of this extracted sparse regions; and an inspection unit that reads this non-inspection regions registered in the storage section and detects the position of particles or deformed patterns present in or on the subject of inspection.
20 . An inspection system comprising:
an inspection device that detects the position of particles or deformed patterns present in or on a subject of inspection; and a device management unit comprising calculation means that extracts the coordinates of a regions where the circuit patterns are sparse from circuit layout data formed on the subject of inspection, storage means that registers as a non-inspection regions the coordinates of this extracted sparse regions, and output means that presents this non-inspection regions registered in the storage means to this inspection device, which is connected through a network.Join the waitlist — get patent alerts
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