Source drive circuit, latchable voltage level shifter and high voltage flip-flop

Abstract

A latchable voltage level shifter is provided. The latchable voltage level shifter comprises: a voltage level shifter receiving an original input signal and generating a high voltage signal according to a timing sequence of a first phase control signal; and a high voltage flip-flop, coupled to the voltage level shifter, receiving the high voltage signal and a second phase control signal, the high voltage flip-flop latching the high voltage signal according to a timing sequence of the second phase control signal and outputting a high voltage output signal. The latchable voltage level shifter can be used in a source drive circuit so as to reduce the layout area and production cost.

1 . A latchable voltage level shifter, comprising: 
 a voltage level shifter, for receiving an original input signal and generating a high voltage signal according to a timing sequence of a first phase control signal; and    a high voltage flip-flop, coupled to said voltage level shifter, for receiving said high voltage signal and a second phase control signal, said high voltage flip-flop latching said high voltage signal according to a timing sequence of said second phase control signal and outputting a high voltage output signal.    
   
   
       2 . The latchable voltage level shifter of  claim 1 , wherein said first phase control signal includes a first clock signal and a second clock signal, and said voltage level shifter includes: 
 a low voltage AND gate, for receiving said original input signal and said first clock signal and performing an AND operation to output a synchronized low voltage signal;    an N-type transistor having a gate, a source and a drain, coupled to said low voltage AND gate and a voltage shifter output terminal, wherein the gate is adapted for receiving said synchronized low voltage signal, the source is coupled to a ground, the drain coupled to said voltage shifter output terminal, wherein said voltage shifter output terminal comprises a voltage level equal to that of said high voltage output signal; and    a P-type transistor, having a gate for receiving said second clock signal, a source coupled to a high voltage level and a drain coupled to said voltage shifter output terminal;    wherein said first clock signal and said second clock signal have a same period.    
   
   
       3 . The latchable voltage level shifter of  claim 1 , wherein said second phase control signal includes a third clock signal and a fourth clock signal, and said high voltage flip-flop includes: 
 a first switch having a first connecting terminal, a second connecting terminal, and a control terminal, said control terminal of said first switch being coupled to said third clock signal, said first connecting terminal of said first switch being coupled to said voltage shifter output terminal, said first switch determining a coupling status between said first connecting terminal of said first switch and said second connecting terminal of said first switch according to said third clock signal;    a second switch having a first connecting terminal, a second connecting terminal, and a control terminal, said control terminal of said second switch being coupled to said fourth clock signal, said first connecting terminal of said second switch being coupled to said second connecting terminal of the first switch, said second switch determining a coupling status between said first connecting terminal of said second switch and said second connecting terminal of said second switch according to said fourth clock signal;    a first high voltage inverter having an input terminal coupled to said second connecting terminal of said first switch and having an output terminal outputting a first output signal; and    a second high voltage inverter having an input terminal coupled to said output terminal of said first high voltage inverter and having an output terminal coupled to said second connecting terminal of said second switch and outputting a second output signal;    wherein said third clock signal and said fourth clock signal have a same period, and one of said first output signal and said second output signal is said high voltage output signal.    
   
   
       4 . The latchable voltage level shifter of  claim 3 , wherein said first switch is an N-type transistor.  
   
   
       5 . The latchable voltage level shifter of  claim 3 , wherein said second switch is an N-type transistor.  
   
   
       6 . The latchable voltage level shifter of  claim 1 , further comprising a capacitor, one terminal of said capacitor being coupled to said voltage shifter output terminal, the other terminal of said capacitor being coupled to said ground.  
   
   
       7 . The latchable voltage level shifter of  claim 1 , wherein said first phase control signal and said second phase control signal have a same period.  
   
   
       8 . A source drive circuit for driving a display panel, comprising: 
 a line latch, for receiving a display data and a first timing sequence signal, said line latch latching said display data according to said first timing sequence signal and outputting an original input signal;    a latchable voltage level shifter, coupled to said line latch, for receiving said original input signal and a second timing sequence signal, said latchable voltage level shifter shifting a voltage level of said original input signal according to said second timing sequence signal and outputting a high voltage output signal;    a digital-to-analog converter, coupled to said latchable voltage level shifter, for receiving said high voltage output signal and converting said high voltage output signal to output a first drive signal corresponding to said high voltage output signal; and    an amplifier, coupled to said digital-to-analog converter and said display panel, for receiving said first drive signal and enhancing a driving ability of said first drive signal to output a second drive signal to drive said display panel.    
   
   
       9 . The source drive circuit of  claim 8 , wherein said second timing sequence signal includes a first phase control signal and a second phase control signal, said latchable voltage level shifter including: 
 a voltage level shifter, for receiving said original input signal and generating a high voltage signal according to a timing sequence of said first phase control signal; and    a high voltage flip-flop, coupled to said voltage level shifter, for receiving said high voltage signal and said second phase control signal, said high voltage flip-flop latching said high voltage signal according to a timing sequence of said second phase control signal and outputting said high voltage output signal.    
   
   
       10 . The source drive circuit of  claim 9 , wherein said first phase control signal includes a first clock signal and a second clock signal, and said voltage level shifter includes 
 a low voltage AND gate, for receiving said original input signal and said first clock signal and performing an AND operation to output a synchronized low voltage signal;    an N-type transistor, coupled to said low voltage AND gate and a voltage shifter output terminal, said N-type transistor having a gate for receiving said synchronized low voltage signal, a source coupled to a ground, a drain coupled to said voltage shifter output terminal, said voltage shifter output terminal having a voltage level equal to that of said high voltage output signal; and    a P-type transistor having a gate receiving said second clock signal, a source coupled to a high voltage level and a drain coupled to said voltage shifter output terminal;    wherein said first clock signal and said second clock signal have a same period.    
   
   
       11 . The source drive circuit of  claim 9 , wherein said second phase control signal includes a third clock signal and a fourth clock signal, and said high voltage flip-flop includes: 
 a first switch having a first connecting terminal, a second connecting terminal, and a control terminal, said control terminal of said first switch being coupled to said third clock signal, said first connecting terminal of said first switch being coupled to said voltage shifter output terminal, said first switch determining a coupling status between said first connecting terminal of said first switch and said second connecting terminal of said first switch according to said third clock signal;    a second switch having a first connecting terminal, a second connecting terminal, and a control terminal, said control terminal of said second switch being coupled to said fourth clock signal, said first connecting terminal of said second switch being coupled to said second connecting terminal of the first switch, said second switch determining a coupling status between said first connecting terminal of said second switch and said second connecting terminal of said second switch according to said fourth clock signal;    a first high voltage inverter having an input terminal coupled to said second connecting terminal of said first switch and having an output terminal outputting a first output signal; and    a second high voltage inverter having an input terminal coupled to said output terminal of said first high voltage inverter and having an output terminal coupled to said second connecting terminal of said second switch and outputting a second output signal;    wherein said third clock signal and said fourth clock signal have a same period, and one of said first output signal and said second output signal is said high voltage output signal.    
   
   
       12 . The source drive circuit of  claim 11 , wherein said first switch is an N-type transistor.  
   
   
       13 . The source drive circuit of  claim 11 , wherein said second switch is an N-type transistor.  
   
   
       14 . The source drive circuit of  claim 9 , further comprising a capacitor, one terminal of said capacitor being coupled to said voltage shifter output terminal, the other terminal of said capacitor being coupled to said ground.  
   
   
       15 . The source drive circuit of  claim 9 , wherein said first phase control signal and said second phase control signal have a same period.  
   
   
       16 . The source drive circuit of  claim 8 , wherein said display panel is a liquid crystal display panel.  
   
   
       17 . A high voltage flip-flop for receiving a high voltage signal, a first clock signal, and a second clock signal, said high voltage flip-flop latching said high voltage signal according to a timing sequence of said first clock signal and said second clock signal and outputting a first output signal and a second output signal, said first output signal and said second output signal having an opposite phase, said high voltage flip-flop comprising: 
 a first switch having a first connecting terminal, a second connecting terminal, and a control terminal, said control terminal of said first switch being coupled to said first clock signal, said first connecting terminal of said first switch being coupled to said high voltage signal, said first switch determining a coupling status between said first connecting terminal of said first switch and said second connecting terminal of said first switch according to said first clock signal;    a second switch having a first connecting terminal, a second connecting terminal, and a control terminal, said control terminal of said second switch being coupled to said second clock signal, said first connecting terminal of said second switch being coupled to said second connecting terminal of said first switch, said second switch determining a coupling status between said first connecting terminal of said second switch and said second connecting terminal of said second switch according to said second clock signal;    a first high voltage inverter having an input terminal coupled to said second connecting terminal of said first switch and having an output terminal outputting a first output signal; and    a second high voltage inverter having an input terminal coupled to said output terminal of said first high voltage inverter and having an output terminal coupled to said second connecting terminal of said second switch and outputting a second output signal;    wherein said first clock signal and said second clock signal have a same period.    
   
   
       18 . The high voltage flip-flop of  claim 17 , wherein said first switch is an N-type transistor.  
   
   
       19 . The high voltage flip-flop of  claim 17 , wherein said second switch is an N-type transistor.