Bonding pad arrangement method for semiconductor devices

Abstract

A variety of pad arrangements are provided for semiconductor devices for reducing the likelihood of bonding failures, particularly those due to shorts, and/or for reducing the difference in length between bonding wires to decrease signal skew during operation of the semiconductor device and improve signal integrity.

1 . A semiconductor device having a plurality of bond pads comprising: 
 a plurality of bond pad pairs, each pair of bond pads including a first bond pad and a second bond pad, wherein    each of the first bond pads is positioned at a first perpendicular distance from a first edge of the semiconductor device; and    each of the second bond pads is positioned at a second perpendicular distance from the first edge of the semiconductor device and separated from a corresponding first bond pad by a third distance in a direction parallel to the first edge of the semiconductor device, wherein:    the first and second perpendicular distances are not identical.    
     
     
         2 . The semiconductor device according to  claim 1 , wherein: 
 the semiconductor device is configured as a pad-on-cell (POC) device including a plurality of memory cell array blocks, and wherein    at least one bond pad pair is arranged on each memory cell array block.    
     
     
         3 . The semiconductor device according to  claim 2 , wherein: 
 each second bond pad is separated from an adjacent non-paired first bond pad by a step distance in a direction generally parallel to the first edge of the semiconductor device.    
     
     
         4 . The semiconductor device according to  claim 3 , wherein: 
 the third distance is an offset distance.    
     
     
         5 . The semiconductor device according to  claim 3 , wherein: 
 the offset distance and the step distance are approximately equal.    
     
     
         6 . The semiconductor device according to  claim 3 , wherein: 
 a ratio between the offset distance and the step distance is at least 1:4.    
     
     
         7 . A semiconductor package comprising: 
 a semiconductor device according to  claim 1;     a lead frame, the lead frame including a plurality of connection regions, the connection regions being arranged along an axis substantially parallel to the first edge of the semiconductor device; and    a plurality of bond wires extending between connection regions of the lead frame and the bond pads, wherein:    the semiconductor device is configured as a pad-on-cell (POC) device that includes a plurality of memory cell array blocks, and further wherein, at least one bond pad pair is arranged over each memory cell array block.    
     
     
         8 . A semiconductor package according to  claim 7 , wherein: 
 the semiconductor device includes 
 a second edge parallel to the first edge;  
 third and fourth edges perpendicular to the first and second edges; and  
 a plurality of third bond pads arranged adjacent at least one of the second, third and fourth edges of the semiconductor device.  
   
     
     
         9 . The semiconductor package comprising: 
 a semiconductor device according to  claim 1 , wherein the semiconductor device is configured as a pad-on-cell (POC) device that includes a plurality of memory cell array blocks separated by a plurality of sense amplifiers and wherein adjacent ones of the bond pads are arranged over at least one memory cell array block.    
     
     
         10 . The semiconductor package according to  claim 9 , wherein: 
 the bond pad pairs are positioned outside a periphery of the sense amplifiers.    
     
     
         11 . The semiconductor package according to  claim 9 , wherein: 
 the semiconductor device includes 
 a second edge parallel to the first edge;  
 third and fourth edges perpendicular to the first and second edges; and  
 a plurality of third bond pads arranged adjacent at least one of the second, third and fourth edges of the semiconductor device.