Double diffused vertical JFET

Abstract

We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a body region above the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

1 - 21 . (canceled)  
   
   
       22 . An method for making an electronic device, comprising 
 a. providing a semiconductor substrate of a first conductivity, having a top surface and a bottom surface;    b. forming a buried layer of a second conductivity near the top surface;    c. forming a first semiconductor layer over the buried layer, doping the region with dopant of the second conductivity;    d. forming in the first layer insulation regions that isolate an island of the first-layer material, the insulation regions having substantially the same thickness as the first layer so the insulation regions reaches the buried layer;    e. forming a second semiconductor layer of the second conductivity over the first semiconductor layer and the insulation regions, portions of the second layer bordering the insulation regions being polycrystalline, portions of the second layer bordering the first layer being mono-crystalline;    f. selectively doping the polycrystalline portions of the second layer with dopant of the first polarity;    g. forming a dielectric layer over a portion of the second layer;    h. forming a third semiconductor layer of the second conductivity over the dielectric layer;    i. removing a portion of the third semiconductor layer to form a source structure and a portion of the second semiconductor layer to form a gate structure; and    j. implanting dopant of the first conductivity into the gate structure and dopant of the second conductivity into the source structure.    
   
   
       23 . The method in  claim 22  in which the semiconductor substrate is silicon.  
   
   
       24 . The method in  claim 22  in which the insulation regions comprise silicon dioxide formed with a STI technique.  
   
   
       25 . The method in  claim 22  in which the first semiconductor layer is about 0.5 micrometers thick and the second semiconductor layer is about 0.2 micrometers thick.  
   
   
       26 . The method in  claim 22  in which the dielectric layer comprises silicon dioxide and silicon nitride.  
   
   
       27 . The method in  claim 22  in which a portion of the dopant implanted into the gate structure diffuses into the mono-crystalline portion of the second semiconductor layer and the first semiconductor layer.  
   
   
       28 . The method in  claim 22  in which the first conductivity is p-type.  
   
   
       29 . The method in  claim 22  in which the first conductivity is n-type.  
   
   
       30 . A method for making an n-channel silicon JFET, comprising 
 a. providing a p-type silicon substrate, having a top surface and a bottom surface;    b. forming a buried layer of mono-crystalline silicon near the top surface, doped with a n-type dopant to a sheet resistance of about 25 ohms per square;    c. forming a 0.5 micrometers silicon mono-crystalline first layer over the buried layer, doping the region with n-type dopant to a concentration of about 1×10 15  dopant ions per cubic centimeter;    d. forming in the first layer insulation regions that isolate islands of the first-layer material, the insulation regions having substantially the same thickness as the first layer so the insulation regions contact the buried layer;    e. forming a 0.2 micrometer silicon second layer over the first layer and the insulation regions, portions of the second layer contacting the insulation regions being polycrystalline silicon, portions of the second layer contacting the first layer being mono-crystalline silicon, doping the second layer with p-type dopant to a concentration of about 1×10 15  dopant ions per cubic centimeter;    f. providing a photoresist pattern uncovering portions of the polycrystalline silicon;    g. implanting into portions of the polycrystalline silicon uncovered by the photoresist pattern with p-type dopant ions;    h. forming a dielectric layer of silicon dioxide and silicon nitride over the second layer;    i. patterning and etching the dielectric layer to form a opening region over the second layer free of the dielectric material;    j. forming a third n-type silicon layer over the dielectric layer;    k. removing a portion of the third silicon layer and a portion of the second silicon layer;    l. implanting p-type dopant into the second silicon regions to form a gate structure; and    m. anneal the silicon substrate at a elevated temperature.