LED fabrication via ion implant isolation

Abstract

A semiconductor light emitting diode includes a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, and a resistive gallium nitride region on the n-type epitaxial layer and adjacent the p-type epitaxial layer for electrically isolating portions of the p-n junction. A metal contact layer is formed on the p-type epitaxial layer. Some embodiments include a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, wherein portions of the epitaxial region are patterned into a mesa and wherein the sidewalls of the mesa comprise a resistive Group III nitride region for electrically isolating portions of the p-n junction. In method embodiments disclosed, the resistive border is formed by forming an implant mask on the p-type epitaxial region and implanting ions into portions of the p-type epitaxial region to render portions of the p-type epitaxial region semi-insulating. A photoresist mask or a sufficiently thick metal layer may be used as the implant mask. In some method embodiments, a mesa is formed in the epitaxial region prior to implantation. During implantation, the epiwafer is mounted at an angle such that ions are implanted directly into the sidewalls of the mesa, thereby rendering portions of the mesa semi-insulating. The epiwafer may be rotated during ion implantation.

1 . A method of defining junctions in light emitting diodes comprising: 
 implanting ions into an epitaxial layer in a diode adjacent a p-n conjunction;    said epitaxial layer having a first conductivity type;    said implanted ions having a type and amount that increase the resistivity of the resulting implanted region and render the implanted region highly resistive.    
   
   
       2 . A method according to  claim 1  wherein the number and type of implanted ions render the material sufficiently resistive such that negligible current flow occurs when a voltage bias is applied to the anodes of adjacent die on a wafer.  
   
   
       3 . A method according to  claim 1  comprising substantially electrically isolating adjacent die.  
   
   
       4 . A method according to  claim 1  comprising increasing the resistivity of the implanted region to at least about 2000 ohm centimeters.  
   
   
       5 . A method according to  claim 1  comprising increasing the resistivity of the implanted region to at least about 10,000 ohm centimeters  
   
   
       6 . A method according to  claim 1  comprising implanting the ions into a pattern that defines an implanted perimeter that is sufficiently doped with the implanted ions to be highly resistive and thereby isolate a defined p-n junction.  
   
   
       7 . A method according to  claim 1  comprising implanting ions into a diode with a silicon carbide substrate.  
   
   
       8 . A method according to  claim 7  comprising implanting ions into a diode on a n-type silicon carbide substrate having a polytype selected from the group consisting of the 2H, 3C, 4H, 6H, 8H, and 15R polytypes of silicon carbide.  
   
   
       9 . A method according to  claim 1  comprising implanting ions into a diode having a substrate selected from the group consisting of sapphire, gallium nitride, magnesium oxide, spinel, silicon, and zinc oxide.  
   
   
       10 . A method according to  claim 1  comprising implanting into a conductive substrate.  
   
   
       11 . A method according to  claim 1  comprising implanting into an insulating substrate.  
   
   
       12 . A method according  claim 1  comprising implanting into a semi-insulating substrate.  
   
   
       13 . A method according to  claim 1  comprising adding a metal contact to the diode and then implanting the diode around the contact so that the contact acts as an implant mask.  
   
   
       14 . A method according to the  claim 13  comprising adding a metal contact with sufficient thickness to prevent ions from reaching the underlying layer.  
   
   
       15 . A method according to  claim 14  comprising forming a metal stack.  
   
   
       16 . A method according  claim 1  comprising implanting the diode through a separate implant mask.  
   
   
       17 . A method according  claim 1  comprising implanting ions selected from the group consisting of nitrogen and phosphorus into a p-type layer of gallium nitride.  
   
   
       18 . A method according to  claim 1  comprising implanting ions selected from the group consisting of hydrogen, helium, aluminum and nitrogen.  
   
   
       19 . A light emitting diode comprising: 
 a silicon carbide substrate,    a first Group III nitride layer on the silicon carbide substrate;    a second epitaxial layer of Group III nitride on the first epitaxial layer and having the opposite conductivity type from the first epitaxial layer; and    a highly resistive perimeter portion in the second epitaxial layer that isolates the p-n junction from undesired electrical contact other than with the ohmic contacts of the diode.    
   
   
       20 . A diode according to  claim 19  wherein said substrate comprises n-type silicon carbide.  
   
   
       21 . A diode according to  claim 20  wherein said first epitaxial layer is n-type gallium nitride and said second epitaxial layer is p-type gallium nitride.  
   
   
       22 . A diode according to  claim 19  further comprising superlattice structures.  
   
   
       23 . A diode according to  claim 19  further comprising at least one multiple quantum well.  
   
   
       24 . A diode according to  claim 19  comprising a substantially transparent silicon carbide substrate.  
   
   
       25 . A lamp comprising the diode according to  claim 19 .  
   
   
       26 . A lamp according to  claim 25  further comprising: 
 a header;    electrical leads; and    a polymeric lens.    
   
   
       27 . A display incorporating the lamp according to  claim 26 .  
   
   
       28 . A light emitting diode according to  claim 19  comprising ohmic contacts to the p-type layer selected from the group consisting of platinum, nickel, gold, titanium, aluminum, silver, and combinations thereof.  
   
   
       29 . A diode according to  claim 19  comprising an ohmic contact to the silicon carbide substrate, said ohmic contact being selected from the group consisting of nickel, platinum, palladium, aluminum, titanium, and combinations thereof.  
   
   
       30 . An ohmic contact according to  claim 29  that is substantially transparent.  
   
   
       31 . A diode according to  claim 30  further comprising a smaller bonding pad added thereto to enhance the flow of current through said diode.  
   
   
       32 . A diode according  claim 19  wherein the ohmic contacts and any attachment metals are selected to reflect and thereby enhance the eventual output of the diode when packaged and in use.  
   
   
       33 . A diode according  claim 19  further comprising a buffer layer between the silicon carbide substrate and the first Group III nitride layer.  
   
   
       34 . A diode according to  claim 33  wherein said buffer layer comprises an aluminum nitride layer.  
   
   
       35 . A diode according to  claim 33  wherein said buffer comprises a graded layer of aluminum gallium nitride that progresses from a higher aluminum nitride concentration near the silicon carbide substrate to a higher gallium nitride concentration at the interface with the gallium nitride epitaxial layers.  
   
   
       36 . A method of electrically defining and isolating a p-n junction in a diode to minimize or avoid undesirable electrical contacts and pathways when the diode is mounted for use and to prevent damage to the junction during separation, the method comprising: 
 depositing an ohmic metal contact layer on a central portion of a p-type epitaxial layer of gallium nitride that is part of a p-n junction;    patterning the metal layer by applying an edge mask to the metal layer, and    thereafter implanting ions into the perimeter portions of the p-type epitaxial layer that are not covered by the edge mask.    
   
   
       37 . A method according to  claim 36  comprising: 
 masking a portion of the ohmic metal layer, removing the remaining exposed ohmic metal contact layer from the epitaxial layer;    implanting the exposed portions of the epitaxial layer with atoms sufficient to increase the resistivity of the exposed portions; and    removing the mask from the ohmic contact to thereby produce high resistivity portions in the p-type layer.    
   
   
       38 . A method according  claim 37  comprising: 
 depositing the ohmic contact and a bond pad prior to the masking step; and    thereafter masking the ohmic contact metal with a photoresist.    
   
   
       39 . A method of isolating junctions in devices comprising: 
 forming a metal stack on at least one epitaxial layer that is part of the junction on a substrate;    depositing an edge mask on the metal stack;    patterning the edge mask using photolithography to form openings that selectively reveal surface portions of the metal stack;    etching the metal stack to selectively reveal surface portions of the epitaxial regions;    removing the edge mask by conventional methods; and    thereafter implanting ions into the exposed portions of the epitaxial region to render the implanted regions highly resistive and to define the junction regions within the structure; and    separating individual die from one another such that defined p-n junction regions are spaced apart from the resulting sidewalls of the separated die and are thereby physically and electrically isolated.    
   
   
       40 . A method according to  claim 39  comprising adding a stack of different metal layers for performing different functions within the diode.  
   
   
       41 . A method according to  claim 39  comprising forming the metal stack by photolithography, deposition and liftoff.  
   
   
       42 . A method of implanting a mesa for isolating a p-n junction comprising tilting a wafer that includes at least one p-n junction with respect to the direction of applied implanting ions so that the implanting ions strike the sides of the mesa at an angle to thereby implant the entire sidewall at once and thereby reduce or eliminate the need for multiple implants.  
   
   
       43 . A method according  claim 42  comprising rotating the wafer during implantation for uniformity.  
   
   
       44 . A method according  claim 42  comprising tilting the wafer carrier by at least about 45°.  
   
   
       45 . A method according to  claim 42  comprising tilting the wafer carrier by at least about 60° to thereby change the implant direction with respect to a direction normal to the mesa sidewall.