US2005193311A1PendingUtilityA1
Content-based video compression
Priority: Oct 25, 1996Filed: Aug 29, 2003Published: Sep 1, 2005
Est. expiryOct 25, 2016(expired)· nominal 20-yr term from priority
H04N 19/537
49
PatentIndex Score
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Claims
Abstract
A video compression method and system including object-oriented compression plus error correction using decoder feedback.
Claims
exact text as granted — not AI-modified1 . (canceled)
2 . An encoder for motion-compensated video, comprising:
(a) first circuitry operable to extract motion data and texture data for a plurality of groups of pixels of input digital video; and (b) second circuitry coupled to an output of said first circuitry, said second circuitry operable to aggregate said motion data and to aggregate said texture data and to insert a resynchronization word between said aggregated motion data and said aggregated texture data.
3 . The encoder of claim 2 , wherein:
(a) each of said group of pixels are the pixels of a 16 by 16 macroblock of pixels of a frame.
4 . The encoder of claim 2 , wherein:
(a) each of said group of pixels are the pixels of a 16 by 16 macroblock of pixels of a frame and lying within an object within said frame.
5 . The encoder of claim 2 , wherein:
(a) each of said group of pixels are the pixels of an 8 by 8 block of pixels of a frame.
6 . The encoder of claim 2 , wherein:
(a) each of said group of pixels are the pixels of an 8 by 8 block of pixels of a frame and lying within an object within said frame.
7 . The encoder of claim 2 , further comprising:
(a) third circuitry coupled to said second circuitry and operable to encode said motion data with a variable length code.
8 . The encoder of claim 2 , further comprising:
(a) third circuitry coupled to said second circuitry and operable to encode said texture data with a variable length code.
9 . The encoder of claim 2 , wherein:
(a) said first circuitry is also operable to extract shape data for an image object which includes said groups of pixels; and (b) said second circuitry is also operable to insert a second resynchronization word which separates said shape data from said aggregated motion data and said aggregated texture data.
10 . The encoder of claim 2 , wherein:
(a) said first circuitry is a programmable processor executing a first program; and (b) said second circuitry is said programmable processor executing a second program.
11 . A decoder for motion-compensated video, comprising:
(a) first circuitry operable to interpret a first sequence of symbols as aggregated motion data of groups of pixels and interpret a second sequence of symbols as aggregated texture data of said groups of pixels wherein said first sequence and said second sequence are separated by a resynchronization word.
12 . The decoder of claim 11 , wherein:
(a) each of said group of pixels are the pixels of a 16 by 16 macroblock of pixels of a frame.
13 . The decoder of claim 11 , wherein:
(a) each of said group of pixels are the pixels of a 16 by 16 macroblock of pixels of a frame and lying within an object within said frame.
14 . The decoder of claim 11 , wherein:
(a) each of said group of pixels are the pixels of an 8 by 8 block of pixels of a frame.
15 . The decoder of claim 11 , wherein:
(a) each of said group of pixels are the pixels of an 8 by 8 block of pixels of a frame and lying within an object within said frame.
16 . The decoder of claim 11 , further comprising:
(a) a variable-length-code decoder coupled to an input of said first circuitry and operable to output said motion data.
17 . The decoder of claim 11 , further comprising:
(a) a variable-length-code decoder coupled to an input of said first circuitry and operable to output said texture data.
18 . The decoder of claim 11 , wherein:
(a) said first circuitry is also operable to interpret a third sequence of symbols as shape data for an image object which includes said groups of pixels, wherein a second resynchronization word separates said shape data from said aggregated motion data and said aggregated texture data.
19 . The decoder of claim 11 , wherein:
(a) said first circuitry is a programmable processor executing a first program.Join the waitlist — get patent alerts
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