Capping layer for a semiconductor device and a method of fabrication

Abstract

Numerous embodiments of a method and apparatus for a capping layer are disclosed. In one embodiment, a method of forming a capping layer for a semiconductor device comprises forming one or more layers on at least a portion of the top surface of a semiconductor device, substantially planarizing at least one of the one or more layers, annealing at least a portion of the semiconductor device, and removing a substantial portion of the one or more layers, using one or more etching processes.

1 - 22 . (canceled)  
   
   
       23 . A semiconductor apparatus, comprising: 
 a substrate of silicon having one or more dopant impurities implanted in at least a portion of the substrate;    a gate dielectric layer formed on at least a portion of the substrate;    a conductive gate formed on the gate dielectric layer;    a capping layer formed on a substantial portion of the exposed surface of the apparatus, wherein the capping layer is substantially at least partially comprised of metal.    
   
   
       24 . The apparatus of  claim 23 , wherein the apparatus comprises one or more integrated circuits (IC).  
   
   
       25 . The apparatus of  claim 23 , wherein at least one of said one or more layers comprises a metal layer.  
   
   
       26 . The apparatus of  claim 23 , wherein at least one of said one or more layers comprises a silicon based layer.  
   
   
       27 . The apparatus of  claim 25 , wherein the metal layer comprises a titanium based layer.  
   
   
       28 . The apparatus of  claim 26 , wherein said silicon based layer comprises silicon dioxide.  
   
   
       29 . The apparatus of  claim 23 , wherein one or more layers comprises a silicon based layer, and one or more layers comprises a metal layer, the method further comprising depositing the silicon based layer on a substantial portion of the exposed surface of the device, and subsequently depositing the metal layer on a substantial portion of the top surface of the silicon based layer to a substantially greater thickness than that of the silicon based layer.  
   
   
       30 . The apparatus of  claim 26 , wherein the silicon based layer is deposited by chemical vapor deposition, and the second layer is deposited by a sputter process.  
   
   
       31 . The apparatus of  claim 23 , wherein the semiconductor device comprises a plurality of partially formed transistors.  
   
   
       32 . The apparatus of  claim 23 , wherein said removing comprises selective removing, wherein the selective removing comprises an etch that removes a substantial portion of the one or more layers, selective to the top surface of the semiconductor device.  
   
   
       33 . The apparatus of  claim 23 , wherein selective removing comprises removing one or more sacrificial layers by using one or more chemicals selected based on the chemicals ability to remove one or more sacrificial layers without substantial removal of other materials on the semiconductor device.  
   
   
       34 . The apparatus of  claim 23 , wherein said removing comprises a wet-etch.  
   
   
       35 . The apparatus of  claim 23 , wherein said wet etch comprises a hydroxide based wet etch.  
   
   
       36 . The apparatus of  claim 23 , wherein said wet etch comprises a sulfuric acid/oxidant based wet etch.  
   
   
       37 . The apparatus of  claim 23 , wherein one or more layers comprises a silicon based layer, and one or more layers comprises a metal layer, the method further comprising removing a substantial portion of metal layer, and subsequently removing a substantial portion of the silicon based layer.