Shallow Trench Isolation Method for a Semiconductor Wafer

Abstract

The present invention relates to a shallow trench isolation method of a semiconductor wafer. This method can prevent dishing phenomenon from occurring over the surface of some wider shallow trenches when a chemical-mechanical polishing method is used to polish the surface of the dielectric material filled in each shallow trench. The method comprises: (1) choosing the shallow trenches with widths greater than a predetermined size and generating at least one dummy in each chosen shallow trench to form a plurality of new trenches with widths less than the predetermined size; (2) covering the surface of the semiconductor wafer with dielectric material to form a dielectric layer; (3) condensing the dielectric layer; (4) polishing the surface of the dielectric layer filled in all the shallow trenches to align the surface of the dielectric material with the surface of the components on the semiconductor wafer.

1 . A method for forming electrically isolating shallow trenches between components on the surface of a semiconductor wafer comprising: 
 (a) providing a semiconductor substrate having at least a first-type trench region used to form a first-type trench, and a second-type trench region used to form a second-type trench, the first-type trench having a width greater than a predetermined value that is greater than a width of the second-type trench;    (b) forming a first photoresist pattern on the semiconductor substrate exposing the first-type trench region and the second-type trench region, and at least a second photoresist pattern on the first-type trench region, the second photoresist pattern having a smaller height than the first photoresist pattern;    (c) etching the first-type trench region and the second-type trench region to form the first-type trench and the second-type trench with the first photoresist pattern as a mask, and to form at least one dummy at a bottom of the first-type trench with the second photoresist pattern as a mask;    (d) stripping the first photoresist pattern and the second photoresist pattern;    (e) forming a dielectric layer over the surface of the semiconductor substrate, wherein the dielectric material of the dielectric layer fills the first-type trench and the second-type trench on the surface of the semiconductor substrate;    (f) condensing the dielectric layer; and    (g) performing a planarization process to polish the surface of the semiconductor wafer for aligning the surface of the dielectric layer inside each of the first-type trench and the second-type trench with the surface of each component on the semiconductor substrate.    
   
   
       2 . The method of  claim 1  further comprising: 
 forming a photoresist layer over the semiconductor wafer; and    utilizing an optical mask of different sets of light penetration capability to perform a photolithography process on the photoresist layer for simultaneously forming the first photoresist pattern and the second photoresist pattern in the photoresist layer.    
   
   
       3 . The method of  claim 1  further comprising: 
 forming a photoresist layer over the semiconductor wafer;    exposing the photoresist layer to light through a first optical mask of different sets of light penetration capability to define the first photoresist pattern;    exposing the photoresist layer to light through a second optical mask of different sets of light penetration capability to define the second photoresist pattern; and    developing the photoresist layer to form the first photoresist pattern and the second pattern.    
   
   
       4 . The method of  claim 1  wherein the predetermined value is about 2 μm.  
   
   
       5 . The method of  claim 1  wherein a preferred height of any dummy is around 300 Å to 500 Å.