Segmented non-volatile memory array with multiple sources having improved source line decode circuitry

Abstract

A flash memory array arrangement having a plurality of erase blocks which can be separately erased. The erase blocks have separate source lines, the state of which is controlled by a source line decoder. In array read, program and erase operations, the source lines of the deselected erase blocks, the blocks that are not being read, programmed or erased, are set to a high impedance level. If a cell in one of the deselected erase blocks is defective in some respect such that the cell is conducting leakage current, the high impedance source line associated with the cell will reduce the likelihood that the defective cell will prevent proper operation of the selected erase block.

1 . A method comprising: 
 forming a plurality of memory cells, the memory cells including a number of sources, each of the sources corresponding to a source of one of the memory cells;    forming a plurality of first source lines coupled to the number of sources;    forming a plurality of second source lines coupled to the first source lines, the memory cells arranged in a plurality of columns, wherein the second source lines are spaced apart by a first number of columns of the plurality of columns; and    forming a plurality of source line straps coupled to the first source lines, wherein the source line straps are spaced apart by a second number of columns of the plurality of columns.    
   
   
       2 . The method of  claim 1 , wherein the first source lines are formed from semiconductor material.  
   
   
       3 . The method of  claim 2 , wherein the second source lines are formed from conductive material.  
   
   
       4 . The method of  claim 3 , wherein the source line straps are formed from conductive material.  
   
   
       5 . The method of  claim 1 , wherein the first source lines and the second source lines are orthogonal.  
   
   
       6 . The method of  claim 1 , wherein the first and second source lines are parallel.  
   
   
       7 . The method of  claim 1 , wherein the first number of columns of the plurality of columns is greater than the second number of columns of the plurality of columns.  
   
   
       8 . A method comprising: 
 forming a first row of memory cells, the memory cells including a number of sources, each of the sources corresponding to a source of one of the memory cells;    forming a second row of memory cells, the memory cells of the second row including a number of sources, each of the sources corresponding to a source of one of the memory cells, wherein memory cells of the first and second rows are arranged in a plurality of columns;    coupling the sources of the memory cells of the first row together using a first source line;    coupling the sources of the memory cells of the second row together using a second source line;    coupling the first source line to the second source using a conductive source line; and    coupling the first source line to the second source using a plurality of source line straps, wherein the source line straps are spaced apart by a number of columns of the plurality of columns.    
   
   
       9 . The method of  claim 8 , wherein the first and second source lines are formed from semiconductor material.  
   
   
       10 . The method of  claim 8 , wherein the conductive source line is formed from a material in which the material includes metal.  
   
   
       11 . The method of  claim 8 , wherein the source line straps are formed from a material in which the material includes metal.  
   
   
       12 . The method of  claim 8 , wherein the number of columns of the plurality of columns is four.  
   
   
       13 . The method of  claim 8 , wherein the first and second source lines are parallel.  
   
   
       14 . The method of  claim 13 , wherein the first and second source lines are orthogonal to the source line straps.  
   
   
       15 . The method of  claim 14 , wherein the conductive source line is parallel with the source line straps.  
   
   
       16 . A method comprising: 
 fabricating a plurality of horizontal source lines in a memory array, each of the horizontal source lines having a resistance per unit length;    connecting the horizontal source lines together using a vertical source line;    connecting the horizontal source lines together at a plurality of horizontal locations using a plurality of vertical source line straps; and    connecting the vertical source line to a global source line through a first plurality of switches.    
   
   
       17 . The method of  claim 16  further comprising: 
 connecting the vertical source line to a source bus through a second plurality of switches.    
   
   
       18 . The method of  claim 16 , wherein the horizontal source lines include semiconductor material.  
   
   
       19 . The method of  claim 16 , wherein the horizontal source lines includes doped polysilicon.  
   
   
       20 . The method of  claim 19 , wherein the vertical source line includes metal.  
   
   
       21 . The method of  claim 16 , wherein the vertical source line includes a material different from a material of the horizontal source lines.  
   
   
       22 . A method comprising: 
 fabricating a first row of flash memory cells, the flash memory cells including a number of sources, each of the sources corresponding to a source of one of the flash memory cells;    fabricating second row of flash memory cells, the flash memory cells of the second row including a number of sources, each of the sources corresponding to a source of one of the flash memory cells, wherein the flash memory cells of the first row and the second row are arranged in a plurality of columns;    coupling the sources of the flash memory cells of the first row together using a first source line;    coupling the sources of the flash memory cells of the second row together using a second source line;    coupling the first source line to the second source using a plurality of conductive source lines, wherein the conductive source lines are spaced apart by a first number of columns of the plurality of columns; and    coupling the first source line to the second source using a plurality of source line straps, wherein the source line straps are spaced apart by a second number of columns of the plurality of columns.    
   
   
       23 . The method of  claim 22 , wherein the first and second source lines are formed from doped semiconductor material.  
   
   
       24 . The method of  claim 23 , wherein the source lines are formed from a material in which the material includes metal.  
   
   
       25 . The method of  claim 24 , wherein the source line straps are formed from a material in which the material includes metal.  
   
   
       26 . The method of  claim 22 , wherein the first number of columns of the plurality of columns is sixteen.  
   
   
       27 . The method of  claim 26 , wherein the second number of columns of the plurality of columns is four.  
   
   
       28 . The method of  claim 22 , wherein the first and second source lines are parallel.  
   
   
       29 . The method of  claim 28 , wherein the first and second source lines are orthogonal to the conductive source.  
   
   
       30 . The method of  claim 29 , wherein the conductive source lines and the source line straps are parallel.  
   
   
       31 . The method of  claim 22  further comprising: 
 forming a number of first switches to couple the conductive source lines to a global source line.    
   
   
       32 . The method of  claim 31  further comprising: 
 forming a number of second switches to couple the conductive source lines to a source bus.    
   
   
       33 . A method comprising: 
 forming a first block of flash memory cells and a second block of flash memory cells, each of the first and second blocks including a number of sources, each of the sources corresponding to a source of one of the flash memory cells;    forming in each of the first and second blocks a plurality of first source lines coupled to the number of the sources;    forming in each of the first and second blocks a number of second source lines coupled to the plurality of first source lines; and    forming in each of the first and second blocks a number of source line straps coupled to the first source lines.    
   
   
       34 . The method of  claim 33 , wherein the second source lines of the first block extend over the second block.  
   
   
       35 . The method of  claim 34 , wherein a length of each of the source line straps of the first block remains within the first block, and wherein a length of each of the source line straps of the second block remains within the second block.  
   
   
       36 . The method of  claim 33 , wherein the flash memory cells of the first and second blocks are arranged in a plurality of rows and a plurality of columns, wherein the second source lines of each of the first and second blocks are spaced apart by a first number of columns of the plurality of columns, and wherein the source line straps of each of the first and second blocks are spaced apart by a second number of columns of the plurality of columns.