Semiconductor integrated circuit having a power-on reset circuit in a semiconductor memory device

Abstract

A semiconductor integrated circuit, which operates in accordance with a power supply voltage and an external clock signal and includes a memory circuit, includes a control circuit, and first and second internal circuits. The control circuit controls the memory circuit in accordance with the power supply voltage. The first internal circuit generates an internal power supply voltage for the control circuit. The second internal circuit generates an internal clock signal for the control circuit. The semiconductor integrated circuit further includes first and second power-on reset circuits. The first power-on reset circuit generates a first power-on reset signal for the first internal circuit after the power supply voltage is generated. The second power-on reset circuit generates a second power-on reset signal for the control circuit. The second power-on reset signal is input to the control circuit after the internal clock signal is input to the control circuit.

1 . A semiconductor integrated circuit which operates in accordance with a power supply voltage and an external clock signal in a semiconductor memory device, comprising: 
 a memory circuit which stores electronic data;    a control circuit which controls the memory circuit in accordance with the power supply voltage;    a first internal circuit which generates an internal power supply voltage for the control circuit, based on the power supply voltage;    a second internal circuit which generates an internal clock signal for the control circuit according to the external clock signal;    a first power-on reset circuit which generates a first power-on reset signal for the first internal circuit after the power supply voltage is generated; and    a second power-on reset circuit which generates a second power-on reset signal for the control circuit, wherein the second power-on reset signal is input to the control circuit after the internal clock signal is input to the control circuit.    
   
   
       2 . The semiconductor integrated circuit according to  claim 1 , wherein the second power-on reset signal is generated from the second power-on reset circuit after the internal clock signal is generated from the second internal circuit.  
   
   
       3 . The semiconductor integrated circuit according to  claim 1 , wherein the second power-on reset signal is generated from the second power-on reset circuit after the first power-on reset signal is generated from the first power-on reset circuit.  
   
   
       4 . The semiconductor integrated circuit according to  claim 1 , wherein the second power-on reset signal is provided to the control circuit after the first power-on reset signal is provided to the first internal circuit.  
   
   
       5 . The semiconductor integrated circuit according to  claim 1 , wherein the second power-on reset circuit is connected with the first power-on reset circuit so as to receive the first power-on reset signal.  
   
   
       6 . The semiconductor integrated circuit according to  claim 1 , wherein the second power-on reset signal is generated after the first power-on reset signal.  
   
   
       7 . The semiconductor integrated circuit according to  claim 1 , wherein the first internal circuit is reset by the first power-on reset signal and the control circuit is reset by the second power-on reset signal.  
   
   
       8 . The semiconductor integrated circuit according to  claim 1 , wherein the second power-on reset circuit comprises: 
 a trimming circuit which controls a timing at which the second power-on reset signal is generated from the second power-on reset circuit.    
   
   
       9 . The semiconductor integrated circuit according to  claim 8 , wherein the trimming circuit includes a fuse which sets the timing at which the second power-on reset signal is generated from the second power-on reset circuit.  
   
   
       10 . The semiconductor integrated circuit according to  claim 1 , wherein the second power-on reset circuit comprises: 
 a frequency dividing circuit which delays the first power-on reset signal to obtain a sub power-on reset signal, wherein the sub power-on reset signal is used to generate the second power-on reset signal.    
   
   
       11 . The semiconductor integrated circuit according to  claim 10 , wherein the frequency dividing circuit comprises: 
 an oscillating circuit which generates a vibration signal;    a data holding circuit which divides a frequency of the vibration signal in accordance with the first power-on reset signal.    
   
   
       12 . The semiconductor integrated circuit according to  claim 10 , wherein the second power-on reset circuit comprises: 
 a trimming circuit which controls a timing at which the sub power-on reset signal is used to generate the second power-on reset signal.    
   
   
       13 . The semiconductor integrated circuit according to  claim 12 , wherein the trimming circuit includes a fuse which sets the timing at which the sub power-on reset signal is used to generate the second power-on reset signal.  
   
   
       14 . The semiconductor integrated circuit according to  claim 1 , wherein the second internal circuit generates a coincident signal which is indicative of a coincidence between a phase of the external clock signal and a phase of the internal clock signal, and wherein the second power-on reset circuit generates the second power-on reset signal based on the coincident signal.  
   
   
       15 . The semiconductor integrated circuit according to  claim 14 , wherein the second power-on reset signal is generated based on the first power-on reset signal.  
   
   
       16 . The semiconductor integrated circuit according to  claim 1 , wherein the power supply voltage is a first power supply voltage, wherein the control circuit and the first internal circuit respectively receive a second power supply voltage which is generated at a rise time which is longer than a rise time at which the first power supply voltage is generated, and wherein the first power-on reset circuit comprises: 
 a first sub power-on reset circuit which generates a first sub power-on reset signal based on the first power supply voltage;    a second sub power-on reset circuit which generates a second sub power-on reset signal based on the second power supply voltage; and    an AND circuit which receives the first and second sub power-on reset signals and then outputs the first power-on reset signal.    
   
   
       17 . A semiconductor integrated circuit which operates in accordance with a power supply voltage and an external clock signal in a semiconductor memory device, comprising: 
 a memory circuit which stores electronic data;    a control circuit which controls the memory circuit in accordance with the power supply voltage;    a first internal circuit connected with the control circuit so as to provide an internal power supply voltage to the control circuit, based on the power supply voltage;    a second internal circuit connected with the control circuit so as to provide an internal clock signal to the control circuit, based on the external clock signal;    a power-on reset circuit connected with the first internal circuit so as to provide a power-on reset signal to the first internal circuit; and    a delay circuit connected between the control circuit and the power-on reset circuit, wherein the delay circuit receives the power-on reset signal and then provides a delayed power-on reset signal based on the power-on reset signal to the control circuit, and wherein the control circuit receives the internal clock signal in advance of the delayed power-on reset signal.    
   
   
       18 . The semiconductor integrated circuit according to  claim 17 , wherein the delayed power-on reset signal is generated from the delay circuit after the internal clock signal is generated from the second internal circuit.  
   
   
       19 . The semiconductor integrated circuit according to  claim 17 , wherein the control circuit receives the delayed power-on reset signal after the first internal circuit receives the power-on reset signal.  
   
   
       20 . The semiconductor integrated circuit according to  claim 17 , wherein the first internal circuit is reset by the power-on reset signal and the control circuit is reset by the delayed power-on reset signal.  
   
   
       21 . The semiconductor integrated circuit according to  claim 17 , wherein the delay circuit comprises P-channel and N-channel MOS transistors connected in series between the power supply voltage and a ground voltage, and wherein gate electrodes of the P-channel and N-channel MOS transistors receive the power-on reset signal, and drain electrodes of the P-channel and N-channel MOS transistors provide the delayed power-on reset signal.  
   
   
       22 . The semiconductor integrated circuit according to  claim 17 , wherein the delay circuit comprises: 
 a trimming circuit which controls a timing at which the delayed power-on reset signal begins to be generated.    
   
   
       23 . The semiconductor integrated circuit according to  claim 22 , wherein the trimming circuit includes a fuse which sets the timing at which the delayed power-on reset signal is generated from the delay circuit.  
   
   
       24 . The semiconductor integrated circuit according to  claim 17 , wherein the delay circuit comprises: 
 a frequency dividing circuit which delays the power-on reset signal to obtain a sub power-on reset signal, wherein the sub power-on reset signal is used to generate the delayed power-on reset signal.    
   
   
       25 . The semiconductor integrated circuit according to  claim 24 , wherein the frequency dividing circuit comprises: 
 an oscillating circuit which generates a vibration signal;    a data holding circuit which divides a frequency of the vibration signal in accordance with the power-on reset signal.    
   
   
       26 . The semiconductor integrated circuit according to  claim 24 , wherein the delay circuit comprises: 
 a trimming circuit which controls a timing at which the sub power-on reset signal is used to generate the delayed power-on reset signal.    
   
   
       27 . The semiconductor integrated circuit according to  claim 26 , wherein the trimming circuit includes a fuse which sets the timing at which the sub power-on reset signal is used to generate the delayed power-on reset signal.  
   
   
       28 . The semiconductor integrated circuit according to  claim 1 , wherein the second internal circuit generates a coincident signal which is indicative of a coincidence between a phase of the external clock signal and a phase of the internal clock signal, and wherein the delay circuit generates the delayed power-on reset signal based on the coincident signal.  
   
   
       29 . The semiconductor integrated circuit according to  claim 17 , wherein the power supply voltage is a first power supply voltage, wherein the control circuit and the first internal circuit respectively receive a second power supply voltage which is generated at a rise time which is longer than a rise time at which the first power supply voltage is generated, and wherein the power-on reset circuit comprises: 
 a first sub power-on reset circuit which generates a first sub power-on reset signal based on the first power supply voltage;    a second sub power-on reset circuit which generates a second sub power-on reset signal based on the second power supply voltage; and    an AND circuit which receives the first and second sub power-on reset signals and then outputs the power-on reset signal.