Source drain and extension dopant concentration

Abstract

A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.

1 - 14 . (canceled)  
   
   
       15 . A semiconductor device comprising: 
 a gate stack formed on the outer surface of a substrate;    first and second sidewall spacers formed on opposing sides of the gate stack;    first and second source drain extension regions formed in the surface of the substrate on opposing sides of the gate stack, the first and second source drain extension regions self-aligned relative to an outward surface of the sidewall spacers; and    first and second sidewall bodies formed on the outward surface of the gate stack, each of the first and second sidewall bodies comprising: 
 a first sidewall-forming layer formed on the outward surface of the first and second sidewall spacers, the first sidewall-forming layer formed by exposing the semiconductor device to a heating cycle in a single wafer reactor; and  
 a second sidewall-forming layer formed on the outward surface of the first sidewall-forming layer in an environment that substantially minimizes dopant loss and deactivation in the first and second source drain extension regions.  
   
   
   
       16 . The semiconductor device of  claim 15 , wherein the first and second sidewall spacers comprise one or more layers of a dielectric material selected from a group consisting of nitride, oxide, oxi-nitride, and silicon dioxide.  
   
   
       17 . The semiconductor device of  claim 15 , wherein the first sidewall-forming layer comprises dielectric material selected from a group consisting of oxide, oxi-nitride, or silicon dioxide.  
   
   
       18 . The semiconductor device of  claim 17 , wherein the semiconductor device is placed in the single wafer reactor for approximately one to two minutes.  
   
   
       19 . The semiconductor device of  claim 15 , wherein the temperature in the single wafer reactor is approximately 600 to 700° C.  
   
   
       20 . The semiconductor device of  claim 15 , wherein the semiconductor device is placed in a batch furnace at a reduced deposition temperature on the order of 500 to 600° C.  
   
   
       21 . The semiconductor device of  claim 15 , wherein the second sidewall-forming layer comprises a dielectric material selected from a group consisting of oxi-nitride or nitride.  
   
   
       22 . The semiconductor device of  claim 15 , wherein the environment comprises bistertiarybutylamino-silane (BTBAS).  
   
   
       23 . The semiconductor device of  claim 15 , wherein the second sidewall spacer layer comprises carbon impurities of a concentration on the order of 3 to 15 percent.  
   
   
       24 . The semiconductor device of  claim 15 , wherein the semiconductor device comprises a transistor.  
   
   
       25 . The semiconductor device of  claim 15 , further comprising first and second source drain regions formed in the surface of the substrate, the first and second source drain regions self-aligned relative to an outward surface of the first and second sidewall bodies.