Channel equalization system and method

Abstract

A system and method for delivering increases speed, security, and intelligence to wireline and wireless systems. The present invention includes a new generation Fast Circuit Switch (packet/circuit) Communication processors and platform which enables a new Internet Exchange Networking Processor Architecture at the edge and core of every communication system, for next generation Web Operating System or Environment (WOE) to operate on with emphasis of a non-local processor or networking processor with remote web computing capabilities.

1 . A system for reducing interference in a communication system, the interference occurring on a data sample signal having a precursor inter-symbol interference (ISI) portion and a post-cursor ISI portion, the system comprising: 
 a first precursor equalizer, for receiving the data sample signal and for performing an equalization operation on said data sample signal to reduce the precursor ISI and to generate an ISI equalized sample signal;    a summer, coupled to said first precursor equalizer, for combining said ISI equalized sample signal and a post-cursor cancellation signal to generate an equalized estimated sample signal;    a slicer, coupled to said summer to receive said equalized estimated sample signal, for generating a detected symbol signal representing a preliminary symbol value of said equalized estimated sample signal;    a precursor canceller, for receiving said equalized estimated sample signal and said detected symbol signal, for further reducing the precursor interference, said precursor canceller having: 
 a finite impulse response filter, for receiving said detected symbol signal and for determining the precursor ISI on said detected symbol signal to generate a precursor cancellation signal,  
 a first delay component to receive said equalized estimated sample signal, for delaying said equalized estimated sample signal by a first amount and to output a delayed equalized estimated sample signal, said first amount corresponding to a delay caused by said slicer and finite impulse response filter, and  
 a DPIC summer to combine said precursor cancellation signal and said delayed equalized estimated sample signal to generate a second output signal representing said data sample signal having a reduced precursor interference portion; and  
   a first post-cursor canceller, for receiving said detected symbol signal, and for reducing the post-cursor interference on said detected symbol signal to generate said post-cursor cancellation signal.