Apparatus inteconnecting circuit board and mezzanine card or cards

Abstract

An apparatus includes a circuit board and a connector assembly which extends outwardly from the circuit board and is capable of simultaneously being connected to a plurality of mezzanine cards.

1 - 35 . (canceled)  
   
   
       36 . An apparatus comprising: 
 an interface card to couple to a structure to mount the interface card on a mezzanine card, the mezzanine card mounted on a circuit board, the structure further comprising: 
 a first signal connector to couple a first communication link to the interface card, the first communication link coupled to at least one device on the circuit board;  
 a second signal connector to couple a second communication link to the interface card, the second communication link coupled to at least one device on the mezzanine card.  
   
   
   
       37 . The apparatus of  claim 36 , wherein the interface card provides a signal interface between the at least one device on the circuit board and at least one device on the mezzanine card.  
   
   
       38 . The apparatus of  claim 37 , wherein the at least one device on the circuit board operates with parallel signals and the at least one device on the mezzanine card operates with serial signals.  
   
   
       39 . The apparatus of  claim 38 , wherein the parallel signals comprise system packet interface level 3 (SPI-3) signals.  
   
   
       40 . The apparatus of  claim 38 , wherein the serial signals comprise PCI-Express signals.  
   
   
       41 . The apparatus of  claim 38 , wherein the serial signals comprise Ethernet signals.  
   
   
       42 . The apparatus of  claim 36 , further comprising a processor mounted on the interface card.  
   
   
       43 . The apparatus of  claim 42 , wherein the processor comprises a processor to provide signal segmentation of signals routed to the circuit board via the second communication link.  
   
   
       44 . The apparatus of  claim 42 , wherein the processor comprises a processor to provide cryptography to signals routed to the circuit board via the second communication link.  
   
   
       45 . The apparatus of  claim 36 , further comprising a field programmable gate array (FPGA) mounted on the interface card.  
   
   
       46 . The apparatus of  claim 36 , wherein the interface card is mounted on the mezzanine card in a parallel orientation to a longitudinal axis, the longitudinal axis along the widest dimension of the interface card.  
   
   
       47 . A system comprising: 
 a circuit board to couple to a backplane mounted on a chassis;    a mezzanine card mounted on the circuit board;    an interface card to couple to a structure to mount the interface card on the mezzanine card, the structure further comprising: 
 a first signal connector to couple a first communication link to the interface card, the first communication link coupled to at least one device on the circuit board via the mezzanine card; and  
 a second signal connector to couple a second communication link to the interface card, the second communication link coupled to at least one device on the mezzanine card.  
   
   
   
       48 . The system of  claim 47 , wherein the interface card provides a signal interface between the at least one device on the circuit board and the at least one device on the mezzanine card.  
   
   
       49 . The system of  claim 48 , wherein the at least one device on the circuit board operates with parallel signals and the at least one device on the mezzanine card operates with serial signals.  
   
   
       50 . The system of  claim 49 , wherein the parallel signals comprise system packet interface level 3 (SPI-3) signals.  
   
   
       51 . The system of  claim 50 , wherein the serial signals comprise PCI-Express signals.  
   
   
       52 . The system of  claim 47 , further comprising a processor mounted on the interface card.  
   
   
       53 . The system of  claim 52 , wherein the processor comprises a processor to provide signal segmentation of signals routed to the circuit board via the second communication link.  
   
   
       54 . The system of  claim 52 , wherein the processor comprises a processor to provide cryptography to signals routed to the circuit board via the second communication link.  
   
   
       55 . The system of  claim 47 , further comprising a field programmable gate array (FPGA) mounted on the interface card.  
   
   
       56 . An apparatus comprising: 
 a mezzanine card to mount on a circuit board and to receive and couple to an interface card, the interface card to provide a signal interface between the circuit board and at least one device on the mezzanine card, wherein the mezzanine card and a received and coupled interface card provide an interface between at least one device resident on the circuit board and at least one device on another mezzanine card mounted to the circuit board.    
   
   
       57 . The apparatus of  claim 56 , further comprising a processor mounted on the interface card, the processor to provide signal segmentation of signals routed to the circuit board via the second communication link.  
   
   
       58 . The apparatus of  claim 56 , further comprising a field programmable gate array (FPGA) mounted on the interface card.  
   
   
       59 . The apparatus of  claim 56 , wherein the interface card is mounted on the mezzanine card in a parallel orientation to a longitudinal axis, the longitudinal axis along the widest dimension of the interface card.