Method for manufacturing semiconductor integrated circuit device

Abstract

A method is used to form a circuit to achieve a high-speed performance and a circuit to attain a high reliability on one and the same substrate, in a semiconductor integrated circuit device containing MIS transistors, in which the gate insulating film is made of a high dielectric constant insulating film. In the method, the high dielectric constant insulating film is removed on the diffusion regions of the MIS transistors in the logic region and I/O region, and suicide layers of a low resistance are formed on the surfaces of the diffusion regions. In the memory region, on the other hand, the silicide layers are not formed on the diffusion regions of the MIS transistors, and the diffusion regions are covered with the high dielectric constant insulating film, thereby preventing damage to the semiconductor substrate during forming of the spacers, silicide layers, and contact holes.

1 . A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: 
 (a) preparing a semiconductor substrate of a first conductivity type, having a logic region and a memory region on a surface thereof;    (b) forming plural trenches on the surface of the semiconductor substrate in the logic region and the memory region, and forming a first insulating film inside the plural trenches;    (c) forming a second insulating film having a relative dielectric constant which is greater than that of the first insulating film on the surface of the semiconductor substrate in the logic region and the memory region;    (d) forming a first conductive piece on the second insulating film in the logic region, and forming a second conductive piece on the second insulating film in the memory region;    (e) introducing first impurities of a second conductivity type, opposite to the first conductivity type, into the surface of the semiconductor substrate, in regions at both ends of the first conductive piece and regions at both ends of the second conductive piece;    (f) removing the second insulating film, except at at least a lower layer of the first conductive piece and at the memory region;    (g) depositing a high melting point metal film to overlie the semiconductor substrate; and    (h) selectively forming a silicide layer in a region between the first conductive piece on the surface of the semiconductor substrate and the first insulating film, in the logic region.    
   
   
       2 . A method of manufacturing a semiconductor integrated circuit device according to  claim 1 , further comprising, between the steps (e) and (f), the steps of: 
 (i) forming a third insulating film to overlie the semiconductor substrate; and    (j) applying anisotropic etching to the third insulating film so as to form a first sidewall insulating film on sidewalls of the first conductive piece, and a second sidewall insulating film on sidewalls of the second conductive piece.    
   
   
       3 . A method of manufacturing a semiconductor integrated circuit device according to  claim 2 , further comprising, between the steps (i) and (j), the step of: 
 (k) introducing second impurities of the second conductivity type, in a region between the first sidewall insulating film on the surface of the semiconductor substrate and the first insulating film, and a region between the second sidewall insulating film and the first insulating film.    
   
   
       4 . A method of manufacturing a semiconductor integrated circuit device according to  claim 1 , further comprising, between the steps (b) and (c), the step of: 
 (1) forming a silicon oxide film on the surface of the semiconductor substrate in the logic region;    wherein, in the logic region, the second insulating film is formed to overlie the semiconductor substrate with intervention of the silicon oxide film, and in the memory region, the second insulating film is formed on the surface of the semiconductor substrate without intervention of the silicon oxide film.    
   
   
       5 . A method of manufacturing a semiconductor integrated circuit device according to  claim 1 , wherein the first and second conductive pieces have a silicon germanium film and a silicon film laminated sequentially from the lower layer.  
   
   
       6 . A method of manufacturing a semiconductor integrated circuit device according to  claim 1 , further comprising the steps of: 
 (m) depositing a third insulating film in the logic region and the memory region;    (n) applying etching to the third insulating film to form a first contact hole in a region between the first conductive piece and the first insulating film, in the logic region;    (o) applying etching to the third insulating film to form a second contact hole in a region between the second conductive piece and the first insulating film, in the memory region; and    (p) forming a third conductive piece in the first contact hole, and a fourth conductive piece in the second contact hole.    
   
   
       7 . A method of manufacturing a semiconductor integrated circuit device according to  claim 6 , wherein a distance between the first conductive piece and the first insulating film in the logic region is larger than a distance between the second conductive piece and the first insulating film in the memory region.  
   
   
       8 . A method of manufacturing a semiconductor integrated circuit device according to  claim 7 , wherein a part of the second contact hole overlaps with the first insulating film in the memory region.  
   
   
       9 . A method of manufacturing a semiconductor integrated circuit device according to  claim 7 , wherein the first and third insulating films are made of a silicon oxide film.  
   
   
       10 . A method of manufacturing a semiconductor integrated circuit device according to  claim 6 , wherein the third insulating film has a silicon nitride film and a silicon oxide film laminated sequentially from the lower layer.  
   
   
       11 . A method of manufacturing a semiconductor integrated circuit device according to  claim 6 , wherein a plane form of the third conductive piece is smaller than a plane form of the fourth conductive piece.  
   
   
       12 . A method of manufacturing a semiconductor integrated circuit device according to  claim 6 , further comprising, between the steps (b) and (c), the step of: 
 (1) forming a silicon oxide film on the surface of the semiconductor substrate in the logic region;    wherein, in the logic region, the second insulating film is formed to overlie the semiconductor substrate with intervention of the silicon oxide film, and in the memory region, the second insulating film is formed on the surface of the semiconductor substrate without intervention of the silicon oxide film.