Timing calibration pattern for SLDRAM

Abstract

Disclosed is an improved start-up/reset calibration apparatus and method for use in an SLDRAM memory device A 2 N bit calibration pattern which is based on a pseudo random sequence is used to calibrate the relative timing of data and a latching clock signal to ensure optimal operation of the memory device. In addition, during calibration of one data path, other nearby data paths may receive in phase, out of phase and/or both in phase and out of phase versions of the calibration pattern so that the data path under calibration is calibrated under conditions which more closely approximate random operating conditions.

1 - 94 . (canceled)  
   
   
       95 . A device for generating a training pattern for use in calibrating a memory device, comprising: 
 an signal path for coupling to a command bus or a flag signal input of said memory device; and    a pattern generator for generating a 2 N  bit repeating pattern on said signal path;    wherein N is a positive integer and said 2 N  bit repeating pattern comprises a predetermined additional bit appended to a (2 N −1) pseudo-random bit sequence.    
   
   
       96 . The device of  claim 95 , wherein said pattern generator comprises: a N-stage shift register, comprising: 
 a shift register input;    a shift register output, coupled to said signal path, for outputting said repeating bit pattern; and    N shifting stages, configured to sequentially shift a bit present at said shift register input to said shift register output through each of said N shifting stages, said N shifting stages including a least significant stage  0  through a most significant stage N−1;    a NOR gate having an output and N−1 inputs, each of said N−1 inputs respectively tapping said shift register at stage  1  through stage N−1;    a first exclusive OR gate having an output and a first input coupled to said output of said NOR gate and a second input coupled to said shift register output; and    a second exclusive OR gate having an output coupled to said shift register input and a first input coupled to said output of said first exclusive OR gate and a second input coupled to tap said shift register at stage  0 .    
   
   
       97 . The device of  claim 96 , further comprising: 
 a reset circuit, configured to set each stage of said shift register to a binary zero state.    
   
   
       98 . The device of  claim 95 , wherein N is equal to 4.  
   
   
       99 . The device of  claim 95 , wherein said device is a memory controller and further includes circuitry for communicating commands and data to at least one memory device.  
   
   
       100 . A memory device, comprising: 
 a control circuit;    N signal paths, wherein N is an integer of at least 1;    N variable delay circuits;    N latches;    a data path;    at least one memory array;    a data circuit, coupled between and configure to transfer information between said data path and said at least one memory array, said data circuit also coupled to said control circuit;    a clock path, coupled to supply a clock signal to said control circuit and said N latches;    wherein 
 said N signal paths are respectively coupled to said N variable delay elements,  
 said N variable delay circuits are respectively coupled to said N latches,  
 said N latches are each coupled to said control circuit; and  
 said control circuit is configured to analyze a bit pattern at the output of said latch circuit and adjust the delay of said variable delay circuit to synchronize data on said data path with a clock signal on said clock path.  
   
   
   
       101 . The memory device of  claim 100 , wherein said N signal paths comprise: 
 a command signal path, for communicating a commands from an external device to said memory device.    
   
   
       102 . The memory device of  claim 100 , wherein said N signal paths comprise: 
 a plurality of command signal paths, forming a command bus for communicating commands from an external device to said memory device.    
   
   
       103 . The memory device of  claim 102 , wherein a number of said plurality of command signal paths is 10.  
   
   
       104 . The memory device of  claim 100 , wherein said N signal paths comprise: 
 a flag signal path, for communicating a 1-bit flag signal to said memory device from an external device.    
   
   
       105 . A memory system, comprising: a memory controller, said memory controller comprising: 
 a data path;    M signal paths; and    a pattern generator for generating a 2 N  bit repeating pattern on at least one of said M signal paths;    wherein N is a positive integer and M is an integer greater than or equal to 1; and    a memory device, said memory device coupled to said memory controller via said data path and said M signal paths, said memory device comprising: 
 a control circuit;  
 M variable delay circuits;  
 M latches;  
 at least one memory array;  
 a data circuit, coupled between and configure to transfer information between said data path and said at least one memory array, said data circuit also coupled to said control circuit;  
 a clock path, coupled to supply a clock signal to said control circuit and said M latches;  
   wherein 
 said M signal paths are respectively coupled to said M variable delay elements,  
 said M variable delay circuits are respectively coupled to said M latches,  
 said M latches are each coupled to said control circuit; and  
 said control circuit is configured to analyze a bit pattern at the output of said latch circuit and adjust the delay of said variable delay circuit to synchronize data on said data path with a clock signal on said clock path.  
   
   
   
       106 . The system of  claim 105 , wherein said pattern generator comprises: 
 a N-stage shift register, comprising: 
 a shift register input;  
 a shift register output, coupled to said signal path, for outputting said repeating bit pattern; and  
 N shifting stages, configured to sequentially shift a bit present at said shift register input to said shift register output through each of said N shifting stages, said N shifting stages including a least significant stage  0  through a most. significant stage N−1;  
   a NOR gate having an output and N−1 inputs, each of said N−1 inputs respectively tapping said shift register at stage  1  through stage N−1;    a first exclusive OR gate having an output and a first input coupled to said output of said NOR gate and a second input coupled to said shift register output; and    a second exclusive OR gate having an output coupled to said shift register input and a first input coupled to said output of said first exclusive OR gate and a second input coupled to tap said shift register at stage  0 .    
   
   
       107 . The system of  claim 106 , wherein said pattern generator further comprises: 
 a reset circuit, configured to set each stage of said shift register to a binary zero state.    
   
   
       108 . The system of  claim 105 , wherein N is equal to 4.  
   
   
       109 . The system of  claim 105 , wherein said M signal paths comprise a plurality of command paths forming a command bus.  
   
   
       110 . The system of  claim 105 , wherein said M signal paths comprise a flag signal path for communicating a 1-bit flag between said memory controller and said memory device.