Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device
Abstract
By using a small number of needles and contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A packaging structure in which, for example, a volatile memory chip and a nonvolatile memory chip are formed is assembled in accordance with a production scheme in which burn-in of each memory chip is performed while still under the state of a semiconductor wafer, and by forming the packaged structure using the good volatile memory chip subjected to burn-in and likewise, also, the nonvolatile memory chip. At this burn-in, contact check is performed by bringing a needle, provided in a burn-in board, into contact with, for example, six test-only signal terminals of a test circuit formed on each semiconductor chip.
Claims
exact text as granted — not AI-modified1 - 8 . (canceled)
9 . A manufacturing method of a semiconductor device, the method comprising:
manufacturing semiconductor wafers including first semiconductor chips; performing burn-in of the semiconductor wafers; cutting the semiconductor wafers to produce a batch of first semiconductor chips; and assembling ones of the first semiconductor chips to manufacture the semiconductor device.
10 . A manufacturing method of a semiconductor device according to claim 9 ,
wherein the performance of the burn-in comprises: performing a contact check for judging electric connection/non-connection between each needle connected to a test apparatus and each terminal provided in each of the first semiconductor chips of the semiconductor wafer.
11 . A manufacturing method of a semiconductor device according to claim 9 ,
wherein the assembling includes: forming a stacked arrangement of the ones of the first semiconductor chips on a substrate in the semiconductor device.
12 . A manufacturing method of a semiconductor device according to claim 11 , wherein the substrate is a wiring substrate.Join the waitlist — get patent alerts
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