Metallization structures for semiconductor device interconnects

Abstract

The present invention provides a metallization structure for semiconductor device interconnects such as a conductive line, including a substrate with a substantially planar upper surface, foundation metal layer disposed on a portion of the substrate upper surface, primary conducting metal layer overlying the foundation metal layer, and metal spacer on the sidewalls of the primary conducting metal layer and the foundation metal layer. The present invention also provides a metallization structure including a substrate with a foundation metal layer disposed thereon, a dielectric layer with an aperture therethrough being disposed on the substrate, where the bottom of the aperture exposes the foundation metal layer of the substrate, and a metal spacer on the sidewall of the aperture and a line or plug of a primary conducting metal fill the remaining portion of the aperture. The present invention also includes methods for making the metallization structures.

1 . A method for making a metallization structure comprising: 
 forming a substrate comprising at least one metal layer on a surface thereof;    forming a dielectric layer over the at least one metal layer;    forming an aperture having at least one sidewall through the dielectric layer to expose a surface of the at least one metal layer;    forming a metal spacer completely flanking the at least one sidewall of the aperture and contacting the least one metal layer; and    forming a conductive layer in a remaining portion of the aperture such that at least a bottom surface of the conductive layer contacts a portion of the at least one metal layer.    
   
   
       2 . The method of  claim 1 , further comprising forming the dielectric layer of silicon oxide.  
   
   
       3 . The method of  claim 1 , further comprising forming the at least one metal layer of Ti, Ta, W, Co or Mo or alloys or compounds thereof, including TaN or TiN.  
   
   
       4 . The method of  claim 3 , wherein the at least one metal layer comprises a first metal layer, and further comprising forming a second metal layer between the first metal layer and the substrate, the second metal layer comprising TiN, TiW, WN, or TaN.  
   
   
       5 . The method of  claim 1 , further comprising forming the at least one metal layer of titanium or titanium nitride.  
   
   
       6 . The method of  claim 1 , further comprising forming the at least one metal layer by vapor deposition.  
   
   
       7 . The method of  claim 6 , further comprising forming the at least one metal layer by CVD, PVD or PECVD.  
   
   
       8 . The method of  claim 1 , further comprising forming the conductive layer by vapor deposition.  
   
   
       9 . The method of  claim 8 , further comprising forming the conductive layer by CVD, PVD or PECVD.  
   
   
       10 . The method of  claim 1 , further comprising forming the at least one metal layer and the metal spacer of the same metal.  
   
   
       11 . The method of  claim 1 , further comprising forming the metal spacer by vapor deposition and directional etching.  
   
   
       12 . The method of  claim 1 , further comprising forming the metal spacer of at least one layer of Ti, Ta, W, Co or Mo, or alloys or compounds thereof, including TaN or TiN.  
   
   
       13 . The method of  claim 1 , further comprising forming the metal spacer of titanium or titanium nitride.  
   
   
       14 . The method of  claim 1 , further comprising forming at least one upper metal layer on the conductive layer.  
   
   
       15 . The method of  claim 14 , further comprising forming the at least one upper metal layer on the conductive layer from Ti, Ta, W, Co or Mo or alloys or compounds thereof, including TaN or TiN.  
   
   
       16 . The method of  claim 14 , further comprising forming the at least one upper metal layer as a plurality of upper metal layers.  
   
   
       17 . The method of  claim 14 , further comprising forming the at least one upper metal layer of titanium or titanium nitride.  
   
   
       18 . The method of  claim 14 , further comprising forming the at least one upper metal layer by vapor deposition.  
   
   
       19 . The method of  claim 18 , wherein the vapor deposition is effected by CVD, PVD or PECVD.  
   
   
       20 . The method of  claim 1 , further comprising removing the dielectric layer and portions of the at least one metal layer not underlying the aperture.  
   
   
       21 . The method of  claim 20 , further comprising removing the dielectric layer by using a hydrofluoric acid wet etch solution or an oxide dry etch process.  
   
   
       22 . The method of  claim 20 , further comprising removing the portions of the at least one metal layer by directional etching.  
   
   
       23 . A method for making a metallization structure comprising: 
 forming a substrate comprising at least one metal layer on a surface thereof;    forming a dielectric layer over the at least one metal layer;    forming an aperture through the dielectric layer to expose a surface of the at least one metal layer;    forming a conducting layer in the aperture such that at least a bottom surface of the conducting layer contacts a portion of the at least one metal layer;    forming at least one upper metal layer overlying the dielectric layer and the conducting layer in the aperture;    removing portions of the at least one upper metal layer overlying the dielectric layer, removing the dielectric layer, and removing portions of the at least one metal layer surrounding the conducting layer to form a multilayer metal structure having at least one sidewall; and    forming a metal spacer flanking the at least one sidewall of the multilayer metal structure.    
   
   
       24 . The method of  claim 23 , further comprising forming the dielectric layer of silicon oxide.  
   
   
       25 . The method of  claim 23 , further comprising forming the at least one metal layer of Ti, Ta, W, Co or Mo or alloys or compounds thereof, including TaN or TiN.  
   
   
       26 . The method of  claim 25 , wherein the at least one metal layer comprises a first metal layer, and further including forming a second metal layer between the first metal layer and the substrate, the second metal layer comprising TiN, TiW, WN, or TaN.  
   
   
       27 . The method of  claim 23 , further comprising forming the at least one metal layer of titanium or titanium nitride.  
   
   
       28 . The method of  claim 23 , further comprising forming the at least one metal layer by vapor deposition.  
   
   
       29 . The method of  claim 28 , further comprising forming the at least one metal layer by CVD, PVD or PECVD.  
   
   
       30 . The method of  claim 23 , further comprising forming the conducting layer by vapor deposition.  
   
   
       31 . The method of  claim 30 , further comprising forming the conducting layer by CVD, PVD or PECVD.  
   
   
       32 . The method of  claim 23 , further comprising forming the at least one metal layer and the metal spacer of the same metal.  
   
   
       33 . The method of  claim 23 , further comprising forming the metal spacer by vapor deposition of a metal layer over the multilayer metal structure and directional etching of the vapor-deposited metal layer.  
   
   
       34 . The method of  claim 23 , further comprising forming the metal spacer of at least one layer of Ti, Ta, W, Co or Mo, or alloys thereof or compounds thereof, including TaN or TiN.  
   
   
       35 . The method of  claim 23 , further comprising forming the metal spacer of titanium or titanium nitride.  
   
   
       36 . The method of  claim 23 , further comprising forming the at least one upper metal layer overlying the dielectric layer from Ti, Ta, W, Co or Mo or an alloy or a compound of any thereof, including TaN or TiN.  
   
   
       37 . The method of  claim 36 , further comprising forming the at least one upper metal layer as a plurality of upper metal layers.  
   
   
       38 . The method of  claim 23 , further comprising forming the at least one upper metal layer of titanium or titanium nitride.  
   
   
       39 . The method of  claim 23 , further comprising forming the at least one upper metal layer by vapor deposition.  
   
   
       40 . The method of  claim 39 , wherein the vapor deposition is effected by CVD, PVD or PECVD.  
   
   
       41 . The method of  claim 23 , further comprising removing the dielectric layer by using a hydrofluoric acid wet etch solution or an oxide dry etch process.  
   
   
       42 . The method of  claim 23 , further comprising removing the portions of the at least one metal layer by directional etching.  
   
   
       43 . The method of  claim 23 , further comprising forming the conducting layer from at least one of aluminum and copper.  
   
   
       44 . The method of  claim 23 , further comprising forming the at least one metal layer, metal spacer, and at least one upper metal layer of the same metal.  
   
   
       45 . The method of  claim 44 , wherein the same metal is Ti.