US2005180205A1PendingUtilityA1

Magnetic random access memory and method of reading data from the same

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Dec 30, 2003Filed: Dec 30, 2004Published: Aug 18, 2005
Est. expiryDec 30, 2023(expired)· nominal 20-yr term from priority
G11C 11/1659G11C 7/14G11C 11/1673G11C 7/062G11C 11/15G11C 11/16
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Claims

Abstract

In a magnetic random access memory (MRAM), and a method of reading data from the same, the MRAM includes a memory cell having one transistor and one magnetic tunneling junction (MTJ) layer, and a reference cell that is operable for use as a basis when reading data stored in the memory cell, wherein the reference cell includes first and second MTJ layers provided in parallel to each other, and first and second transistors provided in parallel to each other, the first and second transistors being respectively connected in series to the first and second MTJ layers. Alternatively, one transistor having a driving capability corresponding to twice a driving capability of the transistor of the memory cell may be substituted for the first and second transistors of the reference cell.

Claims

exact text as granted — not AI-modified
1 . A magnetic random access memory (MRAM), comprising: 
 a memory cell having one transistor and one magnetic tunneling junction (MTJ) layer; and    a reference cell that is operable for use as a basis when reading data stored in the memory cell,    wherein the reference cell includes 
 first and second MTJ layers provided in parallel to each other; and  
 first and second transistors provided in parallel to each other, the first and second transistors being respectively connected in series to the first and second MTJ layers.  
   
   
   
       2 . The MRAM as claimed in  claim 1 , wherein one of the first and second MTJ layers of the reference cell has a maximum resistance of the MTJ layer of the memory cell, and the other of the first and second MTJ layers of the reference cell has a minimum resistance of the MTJ layer of the memory cell.  
   
   
       3 . A magnetic random access memory (MRAM), comprising: 
 a memory cell having one transistor and one magnetic tunneling junction (MTJ) layer; and    a reference cell that is operable for use as a basis when reading data stored in the memory cell,    wherein the reference cell includes 
 first and second MTJ layers provided in parallel to each other; and  
 a first transistor connected in series to the first and second MTJ layers, and  
 wherein a driving capability of the first transistor of the reference cell is twice a driving capability of the transistor of the memory cell.  
   
   
   
       4 . The MRAM as claimed in  claim 3 , wherein one of the first and second MTJ layers of the reference cell has a maximum resistance of the MTJ layer of the memory cell, and the other of the first and second MTJ layers of the reference cell has a minimum resistance of the MTJ layer of the memory cell.  
   
   
       5 . A method of reading data from a magnetic random access memory (MRAM) including a memory cell having one transistor and one magnetic tunneling junction (MTJ) layer, and a reference cell having first and second MTJ layers provided in parallel to each other and first and second transistors provided in parallel to each other, the first and second transistors of the reference cell being connected in series to the first and second MTJ layers, respectively, the method comprising: 
 applying a read current I s  to the memory cell; and    applying a current  2 I s  corresponding to twice the read current to the reference cell.    
   
   
       6 . A method of reading data from a magnetic random access memory (MRAM) including a memory cell having one transistor and one magnetic tunneling junction (MTJ) layer, and a reference cell having first and second MTJ layers connected in parallel to each other and a first transistor which is connected in series to the first and second MTJ layers, the first transistor having a driving capability corresponding to twice a driving capability of the transistor of the memory cell, the method comprising: 
 applying a read current I s  to the memory cell; and    applying a current  2 I s  corresponding to twice the read current to the reference cell.

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