Atomic layer deposition of CMOS gates with variable work functions

Abstract

According to one aspect, a CMOS device includes a PMOS transistor and an NMOS transistor, where each transistor includes a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator. The gate of the PMOS transistor includes a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a first composition having a first work function. The gate of the NMOS transistor includes a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a second composition having a second work function such that the NMOS transistor and the PMOS transistor have threshold voltages of approximately the same magnitude. At least one of the gates includes a ternary metal conductor formed by atomic layer deposition.

1 . A CMOS device, comprising: 
 a PMOS transistor, including a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator, the gate including a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a first composition having a first work function; and    an NMOS transistor, including a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator, the gate including a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a second composition having a second work function such that the NMOS transistor and the PMOS transistor have threshold voltages of approximately the same magnitude,    wherein at least one of the gate for the PMOS transistor and the gate for the NMOS transistor includes a ternary metal conductor formed by atomic layer deposition.    
   
   
       2 . The CMOS device of  claim 1 , wherein the ternary metallic conductor includes Tantalum Aluminum Nitride (TaAlN).  
   
   
       3 . The CMOS device of  claim 1 , wherein the ternary metallic conductor includes Titanium Aluminum Nitride (TiAlN).  
   
   
       4 . The CMOS device of  claim 1 , wherein the ternary metallic conductor includes Titanium Silicon Nitride (TiSiN).  
   
   
       5 . The CMOS device of  claim 1 , wherein the ternary metallic conductor includes Tungsten Aluminum Nitride (WAlN).  
   
   
       6 . The CMOS device of  claim 1 , further comprising a refractory metal on the ternary metallic conductor.  
   
   
       7 . The CMOS device of  claim 1 , further comprising a conductive silicon layer on the ternary metallic conductor.  
   
   
       8 . A CMOS device, comprising: 
 a PMOS transistor, including a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator, the gate including a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a first composition having a first work function; and    an NMOS transistor, including a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator, the gate including a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a second composition having a second work function such that the NMOS transistor and the PMOS transistor have threshold voltages of approximately the same magnitude,    wherein one of the gate for the PMOS transistor and the gate for the NMOS transistor includes Tantalum Aluminum Nitride (TaAlN) formed by atomic layer deposition and the other one of the gate for the PMOS transistor and the gate for the NMOS transistor includes Tantalum Nitride (TaN) formed by atomic layer deposition.    
   
   
       9 . The CMOS device of  claim 8 , further comprising a refractory metal on the ternary metallic conductor.  
   
   
       10 . The CMOS device of  claim 8 , further comprising a conductive silicon layer on the ternary metallic conductor.  
   
   
       11 . A CMOS device, comprising: 
 a PMOS transistor, including a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator, the gate including a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a first composition having a first work function; and    an NMOS transistor, including a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator, the gate including a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a second composition having a second work function such that the NMOS transistor and the PMOS transistor have threshold voltages of approximately the same magnitude,    wherein one of the gate for the PMOS transistor and the gate for the NMOS transistor includes Titanium Aluminum Nitride (TiAlN) formed by atomic layer deposition and the other one of the gate for the PMOS transistor and the gate for the NMOS transistor includes Titanium Nitride (TiN) formed by atomic layer deposition.    
   
   
       12 . The CMOS device of  claim 11 , further comprising a refractory metal on the ternary metallic conductor.  
   
   
       13 . The CMOS device of  claim 11 , further comprising a conductive silicon layer on the ternary metallic conductor.  
   
   
       14 . A CMOS device, comprising: 
 a PMOS transistor, including a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator, the gate including a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a first composition having a first work function; and    an NMOS transistor, including a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator, the gate including a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a second composition having a second work function such that the NMOS transistor and the PMOS transistor have threshold voltages of approximately the same magnitude,    wherein one of the gate for the PMOS transistor and the gate for the NMOS transistor includes Tungsten Aluminum Nitride (WAlN) formed by atomic layer deposition and the other one of the gate for the PMOS transistor and the gate for the NMOS transistor includes Tungsten Nitride (WN) formed by atomic layer deposition.    
   
   
       15 . The CMOS device of  claim 14 , further comprising a refractory metal on the ternary metallic conductor.  
   
   
       16 . The CMOS device of  claim 14 , further comprising a conductive silicon layer on the ternary metallic conductor.  
   
   
       17 . A CMOS device, comprising: 
 a PMOS transistor on a first portion of a substrate having a first impurity doping level and first impurity doping type, including a first source region and drain region having a second impurity doping type, a first channel region having a second impurity doping level of the first impurity doping type disposed between the source and the drain regions to separate them, and a first gate separated from the first channel region by a first gate insulator having a first thickness, the first gate comprising a metallic conductor formed of a plurality of individual layers having a first composition with a first work function to act with the first thickness and second impurity doping level to provide the first gate with a first threshold voltage level;    an NMOS transistor on a second portion of the substrate having a third impurity doping level and the second impurity doping type, including a source region and drain region having the first impurity doping type, a second channel region having a fourth impurity doping level of the second impurity doping type disposed between the source and drain regions to separate them, and a second gate separated from the second channel region by a second gate insulator having a second thickness, the second gate comprising a metallic conductor formed of a plurality of individual layers having a second composition with a second work function to act with the second thickness and fourth impurity doping level to provide the second gate with a second threshold voltage level; and    wherein the NMOS transistor and the PMOS transistor have first and second threshold voltage levels of approximately the same magnitude.    
   
   
       18 . The CMOS device of  claim 17 , wherein at least one of the first and second gates includes a ternary metallic conductor.  
   
   
       19 . The CMOS device of  claim 17 , wherein one of the first and second gates includes a ternary metallic conductor and the other gate includes a binary metallic conductor.  
   
   
       20 . The CMOS device of  claim 17 , further comprising the first impurity doping level equal to the second impurity doping level.  
   
   
       21 . The CMOS device of  claim 17 , further comprising the third impurity doping level equal to the fourth impurity doping level.  
   
   
       22 . The CMOS device of  claim 17 , further comprising the first gate insulator thickness equal to the second gate insulator thickness.  
   
   
       23 . The CMOS device of  claim 17 , further comprising a conductive silicon layer disposed over the ternary metallic conductor.  
   
   
       24 . The CMOS device of  claim 17 , further comprising a refractory metal layer disposed over the ternary metallic conductor.  
   
   
       25 . The CMOS device of  claim 18 , wherein the ternary metallic conductor includes Tantalum Aluminum Nitride (TaAlN).  
   
   
       26 . The CMOS device of  claim 18 , wherein the ternary metallic conductor includes Titanium Aluminum Nitride (TiAlN).  
   
   
       27 . The CMOS device of  claim 18 , wherein the ternary metallic conductor includes Titanium Silicon Nitride (TiSiN).  
   
   
       28 . The CMOS device of  claim 18 , wherein the ternary metallic conductor includes Tungsten Aluminum Nitride (WAlN).  
   
   
       29 . The CMOS device of  claim 19 , wherein the binary metallic conductor includes Tungsten Nitride (WN).  
   
   
       30 . A CMOS device, comprising: 
 a PMOS transistor having a first gate comprising a laminated metallic conductor having at least two different material layers with a first varied composition having a first work function to provide a first threshold voltage level;    an NMOS transistor having a second gate comprising a laminated metallic conductor having at least two different material layers with a second varied composition having a second work function to provide a second threshold voltage level; and    wherein the first and second varied compositions provide the PMOS transistor and the NMOS transistor with first and second threshold voltage levels of approximately the same magnitude.    
   
   
       31 . The CMOS device of  claim 30 , wherein forming at least one of the first and second gates includes a ternary metallic conductor.  
   
   
       32 . The CMOS device of  claim 30 , wherein one of the first and second gates includes a ternary metallic conductor selected from the list including Tantalum Aluminum Nitride (TaAlN), Titanium Aluminum Nitride (TiAlN), Titanium Silicon Nitride (TiSiN), and Tungsten Aluminum Nitride (WAlN) and the other one of the first and second gates includes a binary metallic conductor.  
   
   
       33 . The CMOS device of  claim 30 , further comprising a conductive silicon layer disposed above the ternary metallic conductor.  
   
   
       34 . The CMOS device of  claim 30 , further comprising forming a refractory metal layer on the ternary metallic conductor.