Non-volatile memory cell

Abstract

A memory cell is disclosed. The memory cell includes an N-well, three P-type doped regions formed on the N-type well, a first stacked dielectric layer formed on the N-type well and between a first doped region and a second doped region from among the three P-type doped regions, a first gate formed on the first stacked dielectric layer, a second stacked dielectric layer formed on the N-type well and between the second doped region and a third doped region from among the three P-type doped regions, and a second gate formed on the second stacked dielectric layer.

1 . A memory cell comprising: 
 an N-well;    three P-type doped regions formed on the N-type well;    a first stacked dielectric layer formed on the N-type well and between a first doped region and a second doped region from among the three P-type doped regions;    a first gate formed on the first stacked dielectric layer;    a second stacked dielectric layer formed on the N-type well and between the second doped region and the third doped region from among the three P-type doped regions; and    a second gate formed on the second stacked dielectric layer.    
   
   
       2 . The memory cell of  claim 1  wherein the first stacked dielectric layer can store charges and thereby change the threshold voltage for conducting a P-type channel between the first doped region and the second doped region.  
   
   
       3 . The memory cell of  claim 1  wherein each stacked dielectric layer comprises: 
 a first silicon dioxide layer formed on the N-type well;    a charge storage layer formed on the first silicon dioxide layer; and    a second silicon dioxide layer formed on the charge storage layer.    
   
   
       4 . The memory cell of  claim 3  wherein charge storage layer is composed of silicon nitride (Si 3 N 4 ).  
   
   
       5 . The memory cell of  claim 3  wherein charge storage layer is composed of silicon oxynitride (Si x N y O z ).  
   
   
       6 . A memory cell comprising: 
 a well with first doping type;    a first stacked dielectric layer formed on the said well and between two doped regions with second doping type;    a first gate formed on the first stacked dielectric layer;    a second stacked dielectric layer formed on the said well and between two doped regions with second doping type;    a second gate formed on the second stacked dielectric layer;    a said doped region of the said first stacked dielectric layer is electrically connected with a said doped region of the said second stacked dielectric layer.    
   
   
       7 . The memory cell of  claim 6  wherein the first stacked dielectric layer can store charges and thereby change the threshold voltage for conducting the channel between the first doped region and the second doped region.  
   
   
       8 . The memory cell of  claim 6  wherein each stacked dielectric layer comprises: 
 a first silicon dioxide layer formed on the well with first doping type;    a charge storage layer formed on the first silicon dioxide layer; and    a second silicon dioxide layer formed on the charge storage layer.    
   
   
       9 . The memory cell of  claim 8  wherein charge storage layer is composed of silicon nitride (Si 3 N 4 ).  
   
   
       10 . The memory cell of  claim 8  wherein charge storage layer is composed of silicon oxynitride (Si x N y O z ).