US2005174870A1PendingUtilityA1

SRAM device

Assignee: MATSUSHITA ELECTRIC INDUSTRIAL CO LTDPriority: Jun 28, 2001Filed: Apr 8, 2005Published: Aug 11, 2005
Est. expiryJun 28, 2021(expired)· nominal 20-yr term from priority
H10B 10/00H10B 10/12
46
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Claims

Abstract

In a CMOS type SRAM device having a 6-transistor configuration, only a drive transistor and an access transistor of one unit circuit are designed with a larger size, with the other four transistors having a smaller size.

Claims

exact text as granted — not AI-modified
1 - 9 . (canceled)  
   
   
       10 . An SRAM device, comprising two unit circuits each including a load transistor, a drive transistor, and an access transistor, wherein the load transistor and the drive transistor together form an inverter and the access transistor connects an output of the inverter to a bit line, with the two unit circuits being coupled to each other by connecting an input and an output of the inverter of one unit circuit with those of the inverter of the other unit circuit in a cross-coupled manner, 
 wherein the two unit circuits are asymmetric with each other in terms of threshold voltage of the constituent transistors.    
   
   
       11 . An SRAM device, comprising two unit circuits each including a load transistor, a drive transistor, and an access transistor, wherein the load transistor and the drive transistor together form an inverter and the access transistor connects an output of the inverter to a bit line, with the two unit circuits being coupled to each other by connecting an input and an output of the inverter of one unit circuit with those of the inverter of the other unit circuit in a cross-coupled manner, 
 wherein the two unit circuits are asymmetric with each other in terms of a thickness of a gate oxide film of the constituent transistors.    
   
   
       12 - 14 . (canceled)  
   
   
       15 . An SRAM device, comprising two unit circuits each including a load transistor, a drive transistor, and an access transistor, wherein the load transistor and the drive transistor together form an inverter and the access transistor connects an output of the inverter to a bit line, with the two unit circuits being coupled to each other by connecting an input and an output of the inverter of one unit circuit with those of the inverter of the other unit circuit in a cross-coupled manner, 
 wherein in each of the two unit circuits, the drive transistor and the access transistor have substantially the same channel width and are formed in the same continuous rectangular-shaped active region with no bent portions.

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