Methods and apparatuses for peak detection among multiple signals

Abstract

Digital peak detection among multiple signals, or inputs. In one embodiment, a detection method that includes receiving multiple digitized input signals. For each digitized input signal, the method also includes noting a first data value associated with the digitized input signal at a first time. The method includes comparing the first data values to determine a largest first data value from among the first data values. For each digitized input signal, the method includes noting a second data value associated with the digitized input signal at a second time. The method includes comparing the second data values to determine a largest second data value from among the second data values. The method includes comparing the largest second data value with a threshold data value. The method includes detecting a peak when the largest second data value is greater than the threshold data value, and less than the largest first data value. In other embodiments, devices that includes a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) that is configured to perform at least the steps of this detection method. That is, the FPGA or the ASIC can be provided with logic, or programming, that can be utilized in performing the steps of this detection method.

1 - 19 . (canceled)  
   
   
       20 . A detection method comprising: 
 receiving multiple digitized input signals, each having a data value associated with it; and    detecting that a peak data value has occurred using (a) comparisons of multiple data values to each other over multiple clock periods, and (b) a threshold data value.    
   
   
       21 . The detection method of  claim 20 , further comprising: 
 after a peak has occurred, extracting the data values and storing them in a memory device.    
   
   
       22 . The detection method of  claim 20 , further comprising: 
 digitizing multiple analog input signals.    
   
   
       23 . The detection method of  claim 20 , further comprising: 
 filtering the multiple digitized input signals.    
   
   
       24 . The detection method of  claim 20 , further comprising: 
 receiving at least two analog input signals separated by an interval of no greater than 20 nanoseconds.    
   
   
       25 . A detection method comprising: 
 receiving at least two multiple digitized input signals, each multiple digitized input signal having a data value associated with it; and    detecting that a peak data value has occurred using (a) a comparison of at least two of the data values to each other to determine which is larger, and (b) a threshold data value.    
   
   
       26 . The detection method of  claim 25 , further comprising: 
 after a peak has occurred, extracting the data values and storing them in a memory device.    
   
   
       27 . The detection method of  claim 25 , further comprising: 
 digitizing multiple analog input signals.    
   
   
       28 . The detection method of  claim 25 , further comprising: 
 filtering the multiple digitized input signals.    
   
   
       29 . The detection method of  claim 25 , further comprising: 
 receiving at least two analog input signals separated by an interval of no greater than 20 nanoseconds.    
   
   
       30 . A field programmable gate array (FPGA) configured to at least: 
 receive at least two multiple digitized input signals, each multiple digitized input signal having a data value associated with it; and    detect that a peak data value has occurred using (a) a comparison of at least two of the data values to each other to determine which is larger, and (b) a threshold data value.    
   
   
       31 . The FPGA of  claim 30 , where the FPGA is further configured to at least: 
 after a peak has occurred, extract the data values and storing them in a memory device.    
   
   
       32 . The FPGA of  claim 30 , where the FPGA is further configured to at least: 
 digitize multiple analog input signals.    
   
   
       33 . The FPGA of  claim 30 , where the FPGA is further configured to at least: 
 filter the multiple digitized input signals.    
   
   
       34 . The FPGA of  claim 30 , where the FPGA is configured to process at least two analog input signals separated by an interval of no greater than 20 nanoseconds.